Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: HARI Systems Design


Thanks for your feedback on the 'CMOS at 3.125G' presentation.  
I have some questions/comments on a couple points embedded below:

> 1. Even with the "Emphasis High", the RJ (135 ps)is too high, which is 43%
> of a bit cell time (312 ps) caused by the strip.  The RJ can not be cleared
> by deskew circuit, and will be added to the output of the deskew circuit.
> We may have the excessive link jitter problem in a real system. The BER test
> using an equipment does not include DJ+RJ by other components in a link.
> Referencing data:       (15.01^2 - 11.76^2)^0.5 = 9.64 ps
>                         Therefore: RJ = 14x9.64 = 135 ps

	I think here your are using scope std. dev. numbers
	inappropriately.  The two numbers you chose are actually
	from different semiconductors and different PCB layouts.
	I know of no effective way to get RJ from scope measurements.
> 2. The Pre-emphasis, and Post-emphasis are effective, if the length is
> pre-defined.  In real applications, the strip lengths are all different to
> cause the emphasis technique not only infective, but it may make it worse.
> Unless, we can pre-determine the strip length regardless of any
> application  -- it is impossible to do so.

	Two points:  First, in contrast to past applications, one
	system integrator will 'own' the whole transmission path
	(and the microcode), so tuning equalization is possible.

	Second, even without tuning, compromise settings produce
	much better results than with no equalization.  I had a
	backup slide which I didn't use in the presentation (but
	would be glad to send you) showing low jitter for the same
	emphasis settings thru a short PCB trace (~5").  The 
	theoretical reason for this, I believe, is that the serdes
	output is band-limited, so pre-emphasis has significant 
	effect only over a fairly narrow frequency range.
> 3. Another concern is the PCB space availability.
>         The GbE serdes of 64-pin FQFO package has pin-to-pin pitch of 20 mil (0.5
> mm).  However, the micro strip of a differential pair needs 50 mil spacing
> (35 mil + 15 mil) is far too large  to fit into the 20 mil space available.
> Unless, the 8 differential pairs are spread out around a SERDES chip --
> mixing of high frequency and logic signals is questionable practice.

	I agree that mixing the dif'l pairs with logic lines is
	unwise.  The high speed lines should be close to each
	other.  We already go to finer geometries when escaping
	thru a 50-mil-pitch BGA.  Impedance can be maintained for
	narrower lines on tighter spacing, then wider lines can
	be used after the escape into more open PCB areas for 
	better tolerance and lower resistive loss.

Ed, as you said, from feasibility to qualification is a big gap.
(But not as big a gap as from vaporware to qualification.)  The
gap is mainly attention to detail and the hard work of wringing
out a design.  No leaps of faith are required.  Products can be
delivered at that speed and distance.


 Mike Jenkins               Phone: 408.433.7901            _____     
 LSI Logic Corp, ms/G715      Fax: 408.433.7461        LSI|LOGIC| (R)   
 1525 McCarthy Blvd.       mailto:Jenkins@xxxxxxxx        |     |     
 Milpitas, CA  95035      |_____|