RE: HARI Systems Design
I like your very objective comments, and basiclly I agree with your
reasoning. I am a user; therefore, naturally I am playing my role trying to
find any weakness at this stage of development for further evaluation.
Nevertheless, I have a question on your first comment.
From your presentation, I have no way of knowing those source waveform and
the end waveform were from different transistors. I just assume they were
all from the same set-up, and the waveforms were taken at the same time to
avoid inconsistency in the input and output waveforms comparison.
The worst case RJ was calculated from 14 x Sigma (standard deviation
measured by your scope) as we have been doing for years in industry. I do
not see any question on the equation.
As for the equalization, I agree we may be able to select a value which will
help the long length, but not harm the short one to meet the over all BER
requirements for all lengths. Then, We can say it is better than without an
equalizer. I believe there is room for further analysis and tests.
The isolation of the logic signals and high frequency serial data is a
critical design to separate a reliable product from a noisy product. Of
course, you guys are very knowledgeable in this issue. The reliable design
has to start from the chip pin allocation, then the system designer can
design a reliable PCB layout. I am sure, the semiconductor people will
optimize the chip layout eventfully. Here, I just bring the issue out to
draw chip designer's attention. The higher the differential pair impedance,
the easier for the PC geometry design. The board impedance could be
anywhere from 50 ohms to 150 ohms to be in the realistic range. The PCB
designer will select the optimum values for his own PCB layout.
The FR4 material is not any particularly superior material, as a silver
bullet, for an ultra high frequency PCB applications, which I mentioned in
the other comments. According to my PCB house, over 90% of the PCB houses
in US are already using FR4 material in the market for high data rate
products including my present product. I have ordered several different
lengths of FR4 differential pair samples from my PCB house to revisit the
I believe Hari is viable; however, users have to continue to look for
weaknesses to remove them.
NeytWorth Technologies, Inc.
[mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Mike Jenkins
Sent: Monday, November 29, 1999 10:02 PM
Subject: Re: HARI Systems Design
Thanks for your feedback on the 'CMOS at 3.125G' presentation.
I have some questions/comments on a couple points embedded below:
> 1. Even with the "Emphasis High", the RJ (135 ps)is too high, which is 43%
> of a bit cell time (312 ps) caused by the strip. The RJ can not be
> by deskew circuit, and will be added to the output of the deskew circuit.
> We may have the excessive link jitter problem in a real system. The BER
> using an equipment does not include DJ+RJ by other components in a link.
> Referencing data: (15.01^2 - 11.76^2)^0.5 = 9.64 ps
> Therefore: RJ = 14x9.64 = 135 ps
I think here your are using scope std. dev. numbers
inappropriately. The two numbers you chose are actually
from different semiconductors and different PCB layouts.
I know of no effective way to get RJ from scope measurements.
> 2. The Pre-emphasis, and Post-emphasis are effective, if the length is
> pre-defined. In real applications, the strip lengths are all different to
> cause the emphasis technique not only infective, but it may make it worse.
> Unless, we can pre-determine the strip length regardless of any
> application -- it is impossible to do so.
Two points: First, in contrast to past applications, one
system integrator will 'own' the whole transmission path
(and the microcode), so tuning equalization is possible.
Second, even without tuning, compromise settings produce
much better results than with no equalization. I had a
backup slide which I didn't use in the presentation (but
would be glad to send you) showing low jitter for the same
emphasis settings thru a short PCB trace (~5"). The
theoretical reason for this, I believe, is that the serdes
output is band-limited, so pre-emphasis has significant
effect only over a fairly narrow frequency range.
> 3. Another concern is the PCB space availability.
> The GbE serdes of 64-pin FQFO package has pin-to-pin pitch of 20
> mm). However, the micro strip of a differential pair needs 50 mil spacing
> (35 mil + 15 mil) is far too large to fit into the 20 mil space
> Unless, the 8 differential pairs are spread out around a SERDES chip --
> mixing of high frequency and logic signals is questionable practice.
I agree that mixing the dif'l pairs with logic lines is
unwise. The high speed lines should be close to each
other. We already go to finer geometries when escaping
thru a 50-mil-pitch BGA. Impedance can be maintained for
narrower lines on tighter spacing, then wider lines can
be used after the escape into more open PCB areas for
better tolerance and lower resistive loss.
Ed, as you said, from feasibility to qualification is a big gap.
(But not as big a gap as from vaporware to qualification.) The
gap is mainly attention to detail and the hard work of wringing
out a design. No leaps of faith are required. Products can be
delivered at that speed and distance.
Mike Jenkins Phone: 408.433.7901 _____
LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R)
1525 McCarthy Blvd. mailto:Jenkins@xxxxxxxx | |
Milpitas, CA 95035 http://www.lsilogic.com |_____|