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Re: Give me serial 10GbE or.......


Answer below your questions.

Patrick Gilliland wrote:

> Rich,
> I have questions about some of the assumptions you are making.
> I do not believe all of these assumptions are required to
> achieve the design goal as I understand it to be.  See below
> for detailed comments:
> ------------------------------------------------------
> At 04:10 AM 12/2/99 -0800, you wrote:
> >
> >Pat,
> >
> >The inherent reasons are:
> >
> >a) The ability to locate a transceiver a significant distance (a foot or two)
> >away from the protocol ASIC(s);
> --------------------------------------------------------
> Why locate the transceiver a foot away from the ASIC?
> This is a bad idea even at 1.25Gbit.  In fact, most
> FC and GbE gigabit layouts I have seen have this distance
> managed very well.  Typically, we have seen this separation
> at less than one inch.  There is nothing to be gained by
> separating the ASIC and the transceiver any further, so I
> must say I see nothing compelling in "a)" above.
> ----------------------------------------------------------

The distance I quoted is a maximum. One would not do this if one didn't need to.
However, in large switches/routers, this will indeed be the case for some of the
ports after a "best effort" placement. In any case, you need to provide an
alternative that gets out to a foot or two. I'll make it easy on you and just set
the goal at 8". How can you make a 10-12.5 Gbps trace work at this distance in
FR-4? Even if place your SerDes "on top" of the transceiver, how do you get the 74
signal XMII bus to go 8" back from your SerDes to the MAC? Please consider the
entire path from the MAC to the transceiver in typical 10 GbE switch/routers.

> >b) The ability to use a low-cost technology (e.g. CMOS) to drive the
> >transceiver;
> ----------------------------------------------------------
> I agree with the goal but not the assumption CMOS is the
> only low cost technology enabling this 10G proposal.  There
> is of course now Silicon Germanium technology which has
> already made it's way into a number of commercial trans-
> impedance amplifiers (TIA) and laser drivers.  There is also
> a 10G SONET mux available in SiGe.  GaAs is proven in both
> driver/mux and TIA applications at 10G.
> ------------------------------------------------------------

We're not talking about TIA's and laser drivers that contain handfuls of
transistors. We're talking about quite a bit of digital as well as mixed signal
logic to support wide data paths, SerDes, clock tolerance compensation circuits,
retimers/repeaters, encoding/decoding, state machines to control the link,
management functions, etc.

SiGe is neither low cost nor commonly available at this point in time or the near
future. Remember also that if you place your SerDes "on top" of the transceiver in
order to make the 10-12.5 Gbps trace to it work, then you're stuck with getting 10
Gbps of data from the MAC to the SerDes. What interface are you using here? is it
the Parallel GMII? is it he 622 MHz  16-bit + clock parallel bus? How far can this
interface go in FR-4? Where is the encoding done (8B/10B or scrambling or other)?
If it's in the same ASIC as the Serdes and in GaAs or SiGe, it's not going to
compare favorably with a Hari CMOS solution in terms of power and cost. How do you
later integrate this into the MAC to cut costs? Once again, please consider the
entire path from the MAC to the transceiver in typical 10 GbE switch/routers.

> >c) The ability to use common PCB material to to build 10 Gbps products;
> -------------------------------------------------------------
> No problem.  If we obey the "short is good" rule of RF
> and microwave layout, runs of 1-2 inches can be accomodated
> between the transceiver and the ASICs.  If one makes use of
> buried stripline and blind vias, one extends this a bit further
> without difficulty.  FR-4 will support this just fine.
> -------------------------------------------------------------

I'm out of my league here. I'll leave this to the Ron Miller's, Joel Goergen's,
Michael Fogg's, Rich Feldmen's, etc. for comment.

> >d) The desire to keep microwave technology, if required at all,  isolated
> to a small part of the transceiver;
> -------------------------------------------------------------
> You can not reduce the minimum number or nature of the
> 10G connections inside a transceiver anyway.  You must have
> these connections between photodetector and preamplifier, pre-
> amplifier and post amplifier on the receiver.  The 10G lines
> must also connect laser diode to laser driver.  We also need 10G
> input connections from the laser driver to the outside world
> similar to those needed by the receiver.  So what I am proposing
> is exactly the minimum number of these RF/microwave connections.
> I am absolutely confident in our abilities to accomplish this
> task within the cost goals of the Ethernet community.
> --------------------------------------------------------------

The connection distances you're talking about in an Optical Sub-Assembly are
typically 1 to 2 orders of magnitude shorter than those leaving the OSA and
threading their way back to the system. In addition, you have the luxury of not
having to use FR-4 within the transceiver since transceiver PCB costs are
significantly less than that of a terabit router. You are proposing extending
these 10-12.5 Gbps connections significantly outside the transceiver module
another 1 to 2" back to the SerDes. This layout will be very difficult to control
and a signal integrity nightmare.

Hari offers a cost effective solution with the highest signal integrity due to low
signaling rates (relative to 10-12.5 Gbps) and the shortest high speed
connections. A CMOS chip inside a transceiver can be located very, very close to
the O/E components. Your worst signal integrity problem is with the Hari
interface. This problem is manageable.

> >e) Per port cost. What is your cost target at maturity with the interconnect
> >technology your proposing? Please consider all costs. Is is 3.5X GbE port cost
> >at maturity? If not. This is the primary reason for a low-cost ubiquitous
> >interface like Hari.
> --------------------------------------------------------------
> I have seen the cost targets and the performance goals and I
> do not believe either is unrealistic.  I must point out you
> failed to mention the best argument for HARI on an optical
> PMD - the possible use of MAS.  Though this topic has not been
> debated recently, I believe it has tremendous potential if we
> are able to pull it off.  However, until I see a demonstration,
> I do not think we should burden our transceiver PMD interface
> with HARI.  It does not appear to be necessary except to facilitate
> MAS bandwidth reduction.  I do not believe MAS will be useful
> outside the LAN anyway, so I am not positive about HARI for the
> optical PMD interface.
> -----------------------------------------------------------------

Please allow me to give you an idea of how cost effective a 10 Gbps LAN port can
be in the future. I'll list the port element form the MAC forward and leave you to
run the numbers. Please feel free to compare it to any other

1) 10 GbE MAC is part of a multi-port, say 8-port chip. This is standard 0.25
micron CMOS.
2) The Parallel 10 GMII, PCS, and PMA is integrated into the multi-port chip and
available as a core. No change to the chip technology is required. However
cost/power savings result from going to a better process like 0.18 micron CMOS or
better. The interface out for each port is Hari.
3) The PCB is FR-4, the traces to the transceiver can easily be 20-24".
4) At the end of the trace is a transceiver/PMD. This can be any 10 GbE PMD
including Serial, which I'll focus on to reduce your costs. First we have a CMOS
chip in the transceiver which interfaces with Hari, cleans us the hari and medium
jitter, deskews Hari and the medium , compensates for clock tolerance differences
if multiple clock domains exist, controls Hari's serial lanes, provides management
functions, provide endec functions to achieve the lowest possible line rate,
interfaces to high speed logic signal logic. Optional functions such as smart link
control, Optical Auto-Negotiation , MAS provide significant additional benefits
but I'll ignore those for this exercise. Bottom line is that this is a CMOS chip
which significantly reduces what the remaining high-speed logic needs to do.
Therefore, reducing the complexity and power consumption of that logic.
5) High-speed mux/demux and CDR for 10 Gbps (BiCMOS, SiGe or GaAs)..
6) Optoelectronics including Laser driver, Laser, PIN, TIA and Post-AMP for 10
7) Transceiver packaging and connectorization through a front panel connector.

Given the above. I can envision a 3.5X GbE port cost at maturity by just comparing
to the corresponding GbE bill of materials.

I'd be interested in seeing the bill of material for your proposed transceiver to
MAC path.

> Warmest Wishes,
> Pat Gilliland
> patgil@xxxxxxxxxxx

Best regards,


Richard Taborek Sr.   1441 Walnut Dr.   Campbell, CA 95008 USA
Tel: 408-330-0488 or 408-370-9233           Cell: 408-832-3957
Email: rtaborek@xxxxxxxxxx or rtaborek@xxxxxxxxxxxxx