Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: Give me serial 10GbE or.......

my observation:

At 08:52 PM 02-12-99 -0600, Patrick Gilliland wrote:
>Why locate the transceiver a foot away from the ASIC?
>This is a bad idea even at 1.25Gbit.  In fact, most
>FC and GbE gigabit layouts I have seen have this distance
>managed very well.  Typically, we have seen this separation
>at less than one inch.  There is nothing to be gained by
>separating the ASIC and the transceiver any further, so I
>must say I see nothing compelling in "a)" above.

i believe the issue is not "must be at least 24 inches" but rather "can
be up to 24 inches", and that it is a configuration issue.  i doubt anyone
will impose a long interconnect requirement in this, but you must allow 
for the case where it is not physically possible to have short interconnect 
for both TD and RD.

>I agree with the goal but not the assumption CMOS is the
>only low cost technology enabling this 10G proposal.  There
>is of course now Silicon Germanium technology which has
>already made it's way into a number of commercial trans-
>impedance amplifiers (TIA) and laser drivers.  There is also
>a 10G SONET mux available in SiGe.  GaAs is proven in both
>driver/mux and TIA applications at 10G.

nevertheless, monolithic CMOS is a relatively cheap, mainstream silicon
manufacturing process, and everyone wants it eventually.  SiGe may get 
there one day, but it isn't available to everyone right now.  GaAs solutions
certainly have the bandwidth but consume enormous power (my personal 
bias), are not low-cost or mainstream, and therefore do not qualify.

it is my perception that CMOS GHz-class synthesizers, drivers and receivers 
are something like a year or two out.  remember, it is the history of CMOS that 
while there may not be a circuit solution today there will likely be one later 
once people learn how to exploit the technology properly.

>No problem.  If we obey the "short is good" rule of RF
>and microwave layout, runs of 1-2 inches can be accomodated
>between the transceiver and the ASICs.  If one makes use of
>buried stripline and blind vias, one extends this a bit further
>without difficulty.  FR-4 will support this just fine.

and if there is valid reason why we can't hold interconnect to a uniform 
distance of 1 or 2 inches, should we just abandon everything, or should 
we look for one or more ways to accommodate longer copper?

>[Rich argues for reduced wideband interconnect]
>You can not reduce the minimum number or nature of the
>10G connections inside a transceiver anyway.  [...]

i believe that is Rich's argument as well -- minimal use of microstrip
and stripline is best, they are few in number, they must be well 

>I have seen the cost targets and the performance goals and I
>do not believe either is unrealistic.  I must point out you 
>failed to mention the best argument for HARI on an optical 
>PMD - the possible use of MAS.  Though this topic has not been
>debated recently, I believe it has tremendous potential if we
>are able to pull it off.  However, until I see a demonstration,
>I do not think we should burden our transceiver PMD interface
>with HARI.  It does not appear to be necessary except to facilitate
>MAS bandwidth reduction.  I do not believe MAS will be useful 
>outside the LAN anyway, so I am not positive about HARI for the
>optical PMD interface. 

i don't follow the logic in this one and may have missed more than a 
few messages, so please, someone, correct me if i'm wrong:  HARI does 
not exist to facilitate MAS, HARI is intended to simplify the interface to 
a PMD independently of MAS.  MAS is meant to un-burden (if you like) 
the signal processing demand on drive- and receive-silicon for wide-band
optic communication.  it's my read these two address different problems.