> -----Original Message-----
> From: Tom gandy [SMTP:tgandy@xxxxxxxxxxxxxxxx]
> Sent: Saturday, December 04, 1999 12:35 PM
> To: stds-802-3-hssg@xxxxxxxx
> Subject: Ethernet_to_SONET
> Well I've read Roy Bynum's email and the two WORD documents which were
> linked and downloaded from an ITU FTP site. Interesting stuff and
> for the link. However, I am confused as I don't see any mention of
> problems of mapping from the plesiochronous clock domains of Ethernet
> to +/- 100 ppm) into a Synchronous Hierarchy.
> Of course, there are also issues with Inner Packet Gap shrinkage which
> might cause some problems for the newly defined IPG/Preamble frame.
> A long time ago there was an ANSI effort started to map FDDI frames
> SONET. 100BASE-X directly follows from the physical layer aspects of
> Anyway, Raj Jain's "FDDI Handbook" discusses this whole clocking issue
> the necessary adding and subtracting of bits.
> I'm probably missing something here, but as it stands, I'm confused.
> Tom Gandy
> Industrial Catalyst