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Short Reply to Note by R. Taborek `Hari Byte vs. Word Striping' dated 26 Nov. 1999.

Thank you for sharing your views on some issues related to the Hari
interface. From your referenced  treatise and prior statements, I get the
impression that you are utterly confused about some fundamental as well as
the detailed features of our proposal and you have seriously
misrepresented, probably inadvertently, some aspects of it. Also, with
respect to implementation and circuit questions, your evaluation criteria,
preferences and value scales appear to be in conflict with what I think
experienced designers in this area would normally judge as appropriate. So
it is no surprise that some of your conclusions strike me as outlandish.

Far more disturbing is the fact that you seem to be unable to arrive at a
fair conclusion even where the differences are trivial and simple to
understand. Just as an example, I cite your handling of item 9) Running
Disparity Processing: I think, I am well qualified to evaluate this
function, since for over 2 decades I have been involved with various codec
designs and  many individuals inside and outside my company have asked me
for help . Quite recently, I have designed an 8B/10B codec for 12.5 Gbaud
operation.  So I know for sure, there is no significant difference in the
coding area for byte or word striping, but there is a slight performance
advantage for a word based codec because disparity prediction can be
applied more effectively. With current technologies available to anyone,
just four codecs are required for either case, the only difference is how
they are ganged together which is utterly trivial. As you correctly point
out, at the receiving end of each lane, the bit pattern must be checked for
invalid characters and disparity violations and these circuits are
identical to what is needed for disparity adjustment which requires just
about 50 additional gates and the whole thing is less than a decoder with
checks. It is also obvious that either a byte striped or word striped Hari
can be connected to a scrambled or a 64B/66B coded link with comparable
ease or difficulty. An 8B/10B coded 12.5 Gbaud link is also a viable option
and both Hari versions have to adjust the disparity, but the byte striped
version as currently defined has a known disadvantage because its Idle
structure is ill suited for byte and word alignment at high speeds (It
requires more complex pattern detection circuits with added delay in a
critical area.) My recommendation would be to simply translate the current
Hari Idle for transmission over the 12.5 Gbaud single lane to an Idle word
resembling the Fibre Channel Idle . Based on these  verifiable  facts, it
is hard to understand how you can justify the attribution of a bonus point
for the current Hari version.

We will reply soon with details and attempt to present a more balanced
perspective on other issues as well.

Albert Widmer
Phone:  914 945-2047                        email: widmer@xxxxxxxxxx
IBM T.J.  Watson Research Center
P.O. Box 218
Yorktown  Heights, New York, 10598-0218