Is HARI "THE" PMD interface ?
I believe you have finally crystallized what a number
of people are thinking about this issue. I believe
Ed Chang also made some comments along this line. The
confusion is real about whether HARI is indeed a PHY
specification or not. I happen to agree the backplane
designers are free to use whatever works best, but I
doubt we should propose it as a PHY interface standard
until the PHY itself is defined.
I saw a lot of confusion in the presentations of what Hari is intended
for. One presentation used Hari as a backplane interconnect. There is
confusion on the reflector. There IS a lot of "support" for Hari from
vendors that want to stay on the good side of a particular vendor.
Otherwise, I suspect that there is a lot of concern about the way that
Hari has been brought to the HSSG.
When Hari was first introduced at York, I thought that it was a proposal
for a an XGMII. While I did not actively support it, as a XGMII it did
not preclude the existence of other PHYs. It could be modified to
incorporate a pacing mechanism between a PHY and the MAC. The PHY would
still implement the PCS/PMA/PMD for what ever standard the Task Force
decided on, even the one from Korea.
As far as I am concerned, any chip maker/system designer that wants to
use Hari can. I just don't want to see it standardized as the PCS to
PMD interconnect, even as an optional. The HSSG is not the correct
forum to be doing implementation practices or standards. That was one
of the things that was impressed on me at the June meeting. There is
enough disparity between the PHYs to cause a major rift if a PHY
implementation standard is decided on before the PHYs are even defined.
Unless a particular vendor is doing their best to back door a PHY
standard before the Task Force is even in place, there is no need to
decide on implementation practices before the PHYs are fully defined.