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Re: Hari Byte vs. Word striping


I'd like to respond to your points individually below: 

mritter@xxxxxxxxxx wrote:
> Richard Dugan,
> I have seen both of your postings of 12/10, one where you agree with the
> points Al Widmer has made technically, then another where you consider the
> byte vs. word case a draw.  Let me point out, firstly, that the
> implications of Al Widmer's points, with which you agreed, are:
>        1)  Byte striping will have more complex high-speed logic than the
> word striping,

I disagree, and so apparently does Richard. Please prove your assertion by a
means acceptable to this standards body such as product, prototype,
illustration, etc. Otherwise, your claims by emphatic assertion are just that.  
>        2)  Byte striping will therefore have higher power consumption than
> word striping (to be quantified),

If the SerDes for Byte-Striping is the same, or significantly reduced in
size/structure since it does not need to handle Words on each lane, than a
Byte-Striping SerDes will use less power. Richard already alludes to the fact
that the Striping granularity is independent of the SerDes. I agree. You claim
that an advantage of Word-Striping is that existing SerDes designs need not be
changed. In my note establishing evaluation criteria for striping, I have
identified #6 SerDes Width and #13 Power Consumption to be advantages for
Byte-Striping. Please reference that note. In summary, the SerDes width of 20 or
40-bits seemingly requiring for Word-Striping will clearly consume more power
than a 10-bit (byte-wide) SerDes. The SerDes and associated PLL/DLL circuitry is
where most Hari power will be consumed. Don't you agree?

If not, Please prove your assertion by a means acceptable to this standards body
such as product, prototype, illustration, etc.
>        3)  Byte striping makes link deskew monitoring much more complex,
> and requires unique initialization sequence to deskew fully,

Once again, I disagree. Please prove your assertion by a means acceptable to
this standards body such as product, prototype, illustration, etc. The 10 GbE
link deskew and simple Idle pattern (much simpler than required for Fibre
Channel) proposed in Kauai by Howard Frazier, Jonathan Thatcher, Richard Dugan,
Ali Ghiasi, myself and the many proponents of Hari should be ample indication
that your assertions are unfounded.

>        4) All of the above mean that testing of the byte-striped Hari will
> be more difficult and yield will be lower (how much?) than for word
> striping.

I won't bother repeating myself for the fourth time.

> At the 10 G Fibre Channel meeting just this week, the byte striping
> presentation included frank statements agreeing with the first three points
> above (presented by the Hari group, not me!), and the logical conclusion of
> these points is point number 4.

Let's set the record straight. There was no 10 G Fibre Channel Meeting "this
week" (now last week). NCITS T11, which includes all Fibre Channel projects,
held its Plenary week in Reno, NV the week of Dec 6-10, 1999. During a joint
session of T11.2 )FC Physical) and T11.3 )FC Interconnects) on Wednesday,
December 8, 1999 at 1:00 PM, a proposal was made to establish a 10 Gigabit Fibre
Channel (10 GFC) Working Group. In addition, Hari was introduced to joint group.
No technical presentations or proposals were made to this group.

On Thursday, December 9, 1999 during the T11 Plenary, it was formally decided to
establish the 10 GFC WG and start working on objectives. Your presentation,
essentially the same as presented in Kauai, was presented to the T11.3 FC-FS
Working Group, the same forum to which Word-Striping proposals for Fibre Channel
was made for purposes such as aggregating four 2G Fibre Channel links.

The 10 GFC WG will next meet during the next T11 Plenary week on February 14-18
in Huntington Beach, CA. A call for objectives and proposals for 10 GFC will be
made prior to that meeting by the Joint T11.2/T11.3 chair, Jeff Stai. I will be
asking for presentation time for a Byte-Striping Hari-based proposal for 10 GFC
at that meeting.


Best Regards,

> To me, this does not seem to be "a draw,"
> it seems that word striping has considerable advantages for all concerned-
> perhaps even those who have begun trying to design the byte striping
> hardware.  The only plus of byte striping is lower latency, which is not
> important for any of the proposed 10 Gb EN media options, since the added
> latency is insignificant compared to even the shortest media latencies.
> Could you please explain why you feel that the byte vs. word has come to a
> "draw" ?
> Mark B. Ritter
>   Manager, Communication Link Design
>   Room 36-107
>   IBM T.J. Watson Research Center
>   P.O. Box 218
>   Yorktown Heights, NY.  10598
>        phone: (914) 945-2170
>        fax      :                  -1974
>        dept. secretary   -3498
> "DUGAN,RICHARD (HP-SanJose,ex1)" <richard_dugan@xxxxxxxxxxx> on
> 12/10/99 08:34:46 PM
> Sent by:  owner-stds-802-3-hssg@xxxxxxxx
> To:   "'stds-802-3-hssg@xxxxxxxx'" <stds-802-3-hssg@xxxxxxxx>
> cc:
> Subject:  Hari Byte vs. Word striping
> Now that the dust has settled a bit, I would like to declare the match a
> draw (at least from our point of view).  It seems that both sides have some
> advantages and disadvantages, but as a serdes vendor we don't see any
> knockout punch. There are other more difficult problems to be solved.
> With that in mind, it seems like there is no compelling reason to change
> from the original byte striped proposal.
> - Regards,
> Richard Dugan
> Agilent Technologies


Best Regards,

Richard Taborek Sr.         Tel: 408-330-0488 or 408-370-9233       
Chief Technology Officer                   Cell: 408-832-3957
nSerial Corporation             Email: rtaborek@xxxxxxxxxxxxx  
2500-5 Augustine Dr.           Alt email: rtaborek@xxxxxxxxxx 
Santa Clara, CA 95054