Reply to note by R. Taborek, `Hari Byte vs. Word Striping', dated 26 Nov 1999
We have learned that some subscribers have not received the note below, and
it never made it to the Email Reflector Archive for unknown reasons. So
here it is again, with apologies to those who have received it previously.
This is a note in reply to Rich Taborek's note (26 Nov 1999) on Byte vs.
Important Characteristics of the word-striped Hari Proposal
A list of principal reasons, why I believe a word-striped Hari is the most
attractive technical solution for the 10 GbE and Fibre Channel application
is summarized here:
1) The word-striped Hari keeps a 4-byte transport structure intact
through all levels and configurations of data transmission with a uniform
orientation (parallel/serial). (For idles, skips, and initialization, the
byte-striped proposal uses on the 4 lanes a combination of parallel and
serial formats in a single transport layer resulting in a two dimensional
operating space, which is at the root of many of the difficulties for
defining suitable `code blocks' and arriving at simple models and
implementations). The word-striped proposal does not allow any parallel
formats in the serial transmission domain. No deviations from this
structure are needed for the benefit of synchronization (byte, word,
frequency compensation) regardless of the number of transmission lanes. So
any protocol which is compatible with the 4-byte wide structure can
readily be accommodated and others can be made compatible without much
pain, as is the case for 10 GbE framing per Howard Frazier, without its
skip and idle definitions.
2) It has a much wider native skew tolerance making special deskew
circuits superfluous and saving significant high-speed (baud and fractional
baud intervals) circuit complexity and associated power consumption.
3) Much simpler, less state-ful logic, much cleaner interfaces, and
more flexibility in mapping link protocols onto the link coding, fewer
special cases of the "can remove X bytes if and only if they a re preceded
Y bytes and followed by Z bytes" variety.
4) Idle or skip insertion is done independent of the coding, and
independent of the number of lanes ( An idle is a 4-byte word inserted into
the stream of 4-byte words whenever necessary -- no variation/dependency in
format vs. number of lines in the interface). These operations are done in
the stream of deserialized, word boundary aligned words, in coded or
5) Frame format and coding (except for disparity control) independent
of the number of lanes.
6) Word sync between every packet with minimum Ethernet IPG.
7) Much greater flexibility in control sequences -- don't run out of
control characters, since link control is done with control words instead
of a single K character.
8) Almost all the logic is done on a per-word basis, rather than a
per-byte basis. -- Simpler logic clocking.
9) It's very intuitive, and easier to describe, construct, and
simulate than the per-byte interfaces.
10) Doing line de-crossing (i.e. to get lines 0-3 to connect to lines
3-0 in mirrored order, with the de-crossing done inside the chips) is
trivially easy, adds 0 ns of extra latency, and adds a very few extra
gates. Line de-crossing on the chip can save significant area on the card
in complex systems.
Detailed Reply to Rich Taborek's note `Hari Byte vs. Word Striping', dated
26 Nov 1999
See the web sites below for a full reply to Mr. Taborek's long note,
including some additional foils on "staggered word striping" as mentioned
verbally by Dr. Ritter at the Kauai meeting. (The files were too large as
formatted to be reflected; they do NOT have the new worm !)
The two files are located at the following URLs:
Albert Widmer Phone: 914 945-2047 Email:
IBM T.J. Watson Research Center
Yorktown Heights, NY 10598-0218