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Hari KrishMAS


I can sense a little frustration building in your 
last posting.  It is certainly not my intention to
cause you any additional stress along with your many
other responsibilities.  My object in commenting is
not to convince you to withdraw your proposal, nor is it
to put forth an entirely new proposal.  I only hope to 
clarify certain issues and perhaps allow you and others
who support HARI to modify, amend, and progress your
ideas if you so desire.

I believe there might be a broader acceptance of your 
proposed architecture if some of the difficulties I have
highlighted are properly addressed.  I see this process
as brainstorming, and therefore take no offense when my
ideas do not sprout as seeds in the fertile loam of your

Please do not interpret my disagreement with your wishes
to place HARI into the optical PMD as a negative comment
on the thorough and detailed job you have done in making
a case for both HARI and MAS.


>IEEE P802.3ae is an open forum. I have, jointly with many proponents,
>and support Hari an optional interface for LAN PHY PMDs. Please feel free to
>submit your ideas as a counter-proposal to Hari. Your next opportunity
will be
>in Dallas in January. According to the chair's schedule, you have until July,
>2000 to bring forth your proposal. It does little good to only argue your
>position here. i doubt that the Hari proposal will be withdrawn.
>I've been a bit busy starting a company, starting the 10 Gigabit Fibre
>Project, working on Hari, addressing Hari striping granularity issues,
>Serial PMD architecture, playing with my kids, etc. I still view MAS as
the most
>cost effective means of attaining higher data rates over optics relative
to WDM
>and using parallel fibers, both of which increase the number of O/E elements
>and/or medium fibers. I'm not backing away from MAS by a long shot...
Don't you
>worry :-)

Glad to hear you are still the champion of MAS.  I am
looking forward to the demonstration.  I hope you will
consider the 1Gbit/PAM10 option on 1300nm I outlined
earlier.  I believe there are serious problems of laser
safety for a 850nm MAS transmitter.
>> I am not sure what the choices are here interms of the MAC/XMII
>> interface.  Can the XMII/MAC interface benefit from Hari
>> encoding?  I do not see why a HARI or other interface might
>> not be used between SERDES and MAC.  Or maybe a HARI would fit
>> between the SERDES and the optical transceiver.
>Hari IS proposed as the interface between the SerDes (PMA) and the optical
>transceiver (PMD).


I think you have misunderstood me here.  I am suggesting a
HARI interface might be useful chip-to-chip or as an interface
between the SERDES and the MAC.  


>I don't believe that you've answered my question about making 10-12.5 Gbps
>traces work for any practical distance between the SerDes and the optical

I have answered this question adequately.  I believe you are
making a semantic distinction.  My answer is to move whatever
parallel/serial conversion chipset one wants to entertain such
as a HARI outside of the optical PMD device.  Simple.  Distance
is not an issue in this case, because as I have pointed out this
circuit element can be backed up directly against the optical

The real question I would like you to focus on is the flip side.
Why complicate the optical transceiver any further in light of 
the arguments I have already made?  What compelling reasons are 
there which dictate the inclusion of a HARI chip inside the
optical transceiver which can not be solved any other way by
external parallel/serial conversion? 


>> Also, cost effective TIA and laser driver solutions abound
>> in GaAs at the 10Gb/s rate.  I would point you to the web
>> sites of Anadigics, Triquint, and Vitesse.  In my role
>> in developing advanced transceiver designs, I see an ever
>> growing variety of product offerings.  I am also seeing
>> drastic price reductions in mature GaAs building blocks
>> such as TIA, post amplifers, laser drivers.  The SiGe
>> products will have to hit these targets, and the increased
>> availability will prove decisive.
>Once again, the point we were discussion here was the path from the MAC to
>transceiver in typical 10 GbE switch/routers, not TIAs and laser drivers.


I forgot to mention GIGA, Phillips, Arizona Microtek, Microcosm,
Cognet, and a few others.  See my comment above in response to
this.  I believe what we are going back and forth and to and fro
about here is simply a question of partitioning.  I believe some 
of the parallel/serial conversion duties you have assigned to the 
optical PMD belong outside the optical transceiver, however in 
close proximity.


>16X622Mbps carries a clock and can't come close to making Hari distances. The
>other problems are clock distribution and way too many pins to consider
making a
>pluggable module (i.e. >100 pins vs. today's 20 pin GBICs)
>10X1.25Gbps serial clearly goes farther than Hari, but Hari distances are
>sufficient for most applications and Hari distances can be significantly
>extended with careful layout, equalization, etc. 10X will add
approximately 48
>signal and ground pins to a pluggable module and doesn't push CMOS technology
>enough. Therefore, it is not a cost effective alternative to Hari. 


You are making my point about I/O reductions to the optical PMD 
even more emphatically than I was prepared to myself.  The best
definition of a pluggable transceiver has only one high speed,
impedance controlled line at the full line rate.  Otherwise, one
creates a nightmare in terms of cross-channel isolation in the 

>> Please refer to an article in EE Times of November 29, 1999
>> entitled "Lucent to show SiGe process for 10-Gbit Sonet"
>> (Shakespeare never wrote a 10-Gbit Sonnet).
>> It describes a process whereby the SiGe bipolar transistors
>> can be easily added to the existing CMOS process as a
>> selective epitaxial growth.  A mixed technology ASIC with
>> portions capable of 10Gb/s is just what is needed to respond
>> to your concerns above.
>> And, you get your CMOS right where it belongs.
>But it's not going to compare favorably with a Hari CMOS solution in terms of
>power and cost.

I believe it will compare very favorably in terms of power 
consumption.  Of course, the initial cost will be higher, but
2.5Gb/s CMOS is not so inexpensive yet.

>We're going around in circles. I don't believe that you're considering the
>system layout requirements of a multi-port 10 Gigabit Ethernet switch/router.
>1-2" is NOT acceptable.

Again, here I believe we are hung up on a semantic point.
You are implying my position is to require the maximum 
trace lengths on a circuit board to be 1-2".  This is not
the case.  I am solely concerned with the partitioning of
the overly complex optical PMD wherein an optical transceiver
must include a HARI chip and an additional parallel/serial
conversion element.

The 1-2" separation I am referring to would be the maximum
length from the 10Gbit/s serial I/Os on the optical transceiver
to the HARI/SERDES chipset assuming HARI is required at all.


>And how much jitter budget are you leaving for the PMD-to-PMD (medium)
>interface? Hari provides the medium interface with a jitter budget which is
>independent of either of the two SerDes to optical transceiver interfaces.
>is one of the most important, if not THE most important attributes of Hari. 


Jitter independence is nice, but not when the expense is a higher 
overall jitter total.


>I believe that I've pointed out all of the advantages to you individually in
>this note. Please see the Kauai Hari presentations for a good summary.
-------------------Text Omitted-------------------

>That's exactly why MAS, which can be completely implemented in CMOS including
>the laser driver, is such a good idea.


The use of MAS might be better accomplished by separating out
any HARI decode chip and integrating it with a multi-level
copper driver which would enable short distance pluggable
copper connections over coax or other suitable copper media.

A linearized pluggable laser transmitter could then be used
interchangeably with the linear copper pluggable transceiver. 


>> I do not see any value to adding such a CMOS HARI chip
>> inside the optical PMD definition.
>Here are a couple:
>- Lowering the line rate requirements
>- Interfacing directly with existing high-speed Mux/Demux chips
>- Removing as much logic out of the latter elements for future generation
>- Providing the medium interface with the greatest jitter budget
>- Reducing the pin count to the PMD and MAC/PHY enabling configurations
such as
>pluggable SFF transceivers
>- Allowing 20" or longer traces between the PMD and MAC/PHY
>- Enabling low-cost power integrated MAC/PHYs
>- Allowing the continued use of cost effective and common FR-4 PCB


I am on record as favoring bandwidth reduction techniques
on the level of chip-chip-interfaces within the cabinet at
a minimum.  When scalability is an issue, I do not think
MAS or multi-channel techniques offer the advantages of true


>So you're saying that a pluggable self-contained 10 Gbps transceiver with
a port
>cost 3.5X GbE at maturity "does not work for low cost data centric
networks". I
>don't understand how you can compare the 10 GbE port I described above to
a "a
>typical telecom style transceiver". I view it as a highly integrated MAC/PHY
>ASIC and 10XGBIC.  


Beauty is in the eye of the beholder.


>> Low cost transceiver designs are often multi-platform
>> and multi-protocol.  The best way to achieve this goal
>> is what the industry has already decided.  Produce optical
>> transceivers which can handle traffic at a given bit rate
>> or range of bit rates.  Make this same transceiver serve
>> multiple markets as we do today.
>What I've discussed above is multi-protocol. It is usable for Ethernet, Fibre
>Channel, InfiniBand, etc.


Are you implying a solution for chip-chip and backplane connections 
is also ideal for a network?


>> Presently, one transceiver design accomodates the four main
>> markets with only minor testing and tuning variations.
>> The Gigabit Ethernet, Fibre Channel, ATM and central office
>> cross connect (SONET-lite) applications are all leveraging
>> the same set of components and vendors.  All enjoy the
>> benefits of the significant volumes.  I daresay the SONET
>> guys won't be putting the same type of parallel interface
>> into their transceiver definition anytime soon.  This means
>> any 10GbE transceiver with a HARI interface will be a special
>> for the GbE switch market.
>I've put my cards describing a multi-protocol 10 Gbps port architecture on
>table which can meet all HSSG objectives and kick butt in terms of economic
>feasibility. I have yet to see your cards.

I share your objectives.  I apologize if my attempts to improve 
our ideas and understanding has created any difficulties for you.


>> Additionally, your desire to include HARI in the optical
>> PMD does not address the needs of hub and other traffic
>> forwarding equipment designs.  For this application where
>> the design needs to take in 10-12 GbE lines and trunk them
>> up to a 10GbE serial rate, you would require them to first
>> convert each line to the parallel HARI format and then
>> reconvert to serial 10GbE in order to accomodate your
>> wishes to include HARI in the optical PMD.  The trunking of
>> ten 1.25Gbaud lines need not be sucha cumbersome task.
>GbE to 10 GbE translation goes through at least the MAC layer. MAC frame
>are common for these Ethernet speeds. I may be missing your issue, but we
>do add-drop multiplexing in Ethernet. Please clarify.


I am not suggesting we support add-drop.  I am suggesting HARI
may be a lot of extra gates in these instances where everything
can be done on a single chip.

>Oh... I'm sure you'll be back.
>Best Regards,
At least you have better weather out there on the California
coast.  I'm stuck here in Chicago where the temperature is
dropping and the rain is turning to sleet.  Time to go out
and scrape, scrape, scrape.....

Best Wishes for the Holidays,

Pat Gilliland