Re: Feliz Haridad
Pat, my observation:
At 03:22 PM 17-12-99 -0600, Patrick Gilliland wrote:
[...]
I am not advocating PAM10 or any other
multi-level signalling
scheme. It is useful as an in the example I mentioned to
illustrate the greater availability of power at 1300nm. The
accessible power level at 1300nm is greater than at 850nm by
an order of magnitude. This would help in overcoming the SNR
degradations occasioned by MAS.
if by this you refer to eye safety limits then yes, LW lasers are a
better
choice for SNR and that choice can lead to simpler back-end logic
design. but the greater concern is for finding low-cost
silicon technology
that will drive the laser and receive from the TIA at a preferred data
rate.
solve that problem and the cost of adding a bit more backend logic to
improve -effective- (note my emphasis) SNR is, relatively, minor.
[...]
This would put us at -14dBm for the reciever sensitivity. At
present, our minimum transmit power is -10dBm. In order to
maintain a 7dB link budget, we would need to raise this minimum
power to -7dBm.
that is true only if there is no more sophisticated backend
processing
than threshold detect + CDR + formatting for other media. people
have been using FEC for at least the last decade, and i have no
reason to believe it is the only method for improving on channel
SNR.
your concern over power penalty is entirely valid, but we need not
ignore everything that has been learned in Datacom to date.
The following picture illustrates what I have
been suggesting
as an alternative which makes some sense. It helps define the
question of where to partition a little better.
+--------+ XGMII
+-------------+
|
+------->
|
+------+ +-- -----+
| | .
| E S|
Hari |S (E) | | Trans- |
|10 GbE | . | 10 GbE n
e+-------->e (n) | | ceiver |
Medium
| | 36
| D r+-------->r
(D) |1 line | Module |
+--------|
|
|
|
|-------| |
| MAC | . | PCS/PMA e
D+-------->D (e) | 10Gb | (PMD) | 1 fiber
| | .
| c e+-------->e
(c) |
| |
| | .
| s|
FR-4 |s
|
| |
|
+------->
| Trace +------+
+--------+
+--------+ short +-------------+ <=20"
Figure 1 - Recommended partitioning of a transceiver module.
+--------------+
|
|
+-----+ +--------+
| E
S| Hari |S
(E)| | Trans- |
| 10 GbE n e+--------------->e (n)| 1 line | ceiver
| Medium
| D
r+--------------->r (D)|--------| Module +------------>
| MAC/PHY e D+--------------->D (e)| 10Gb
|(PMD) | 1 fiber
| c
e+--------------->e (c)|
| |
|
s| FR-4 PCB |s
|
| |
|
| Traces
+-----+ +--------+
+--------------+ <=20"
Figure 2 - Preferred partitioning of Hari and Integrated MAC/PHY
Chip
within
a 10 GbE Device
it's likely there won't be only one 10Gb line to the transceiver, it's
likely
there will be at least two for the line driver and two from the
receiver.
all of that ignores connection to the Laser and TIA which won't likely be
"zero-length transmission lines" either. if all of these
will operate at a
5GHz line rate, and if any or all of them will be at some non-zero
physical
length, then you will have compounded the EMC problem.
i can fully appreciate a desire to choose one manufacturing
technology
for line drivers & receivers and another for backend processing, but
this
scheme does not appear to be a good choice of circuit partition.
[rich -- independent timing management]
Why do you feel independence is such an
important goal?
I believe the lowest total jitter should be the goal.
achieving that overall goal is much easier if intermediate
sub-blocks
can provide a portion of independent timing management at reasonable
cost. else, you force designers to divide an already small jitter
budget
over relatively many, less-well-behaved components.
i hope this helps.
--
jmw