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Response to R. Taborek note `Hari Debate', Date: Thu, 30 Dec 1999 04:52:36
-0500 (EST)


It is clear that our discourse on Hari matters is not as productive as it
should be. You are still holding on to the very same basic misconceptions
about word-striping as you did at the start when you responded to a
question by Vipul Bhatt "why you like byte-striping over word-striping".
So perhaps we can try one last time to get agreement on some very basic
1) Column-striping at the Hari rate combined with the large skew allowance
requires a special skew control circuit not required for the word-striped
2) The word-striped version can operate indefinitely without any comma
characters after initialization (word sync on all lanes acquired). It does
not require any comparisons or other processing among the several lanes as
you suggest in "doing 128-bit compares on 4 ordered sets at a time",
neither during initialization nor thereafter. This is not mere speculation,
but a technique proven in products. As an example, refer to Widmer et al,
"Single Chip 4 x 500-MBd CMOS Transceiver", IEEE J.Solid-State Circuits,
Dec. 1996, pp. 2004-20014.

If we can not agree on the substance of the above 2 items, it is useless to
discuss any further details.
If you agree, then you also should see that the Fibre Channel format can be
transported without any change at all and the 10GbE format per Frazier is
also compatible with the exception of the Idle. So your assertion that
word-striping requires in the IPG a comma on every lane and that therefore
the minimum IPG is longer than desired is not correct. The expansion of the
number of commas in our example was simply to show that your (and Mr.
Frazier's) belief that that those commas should be present can readily be
accommodated. For the reasons stated in my last note, we like a large
number of commas, but not to the point where they interfere with or detract
from other desirable features or annoy you for other reasons.

You correctly point out that up to three errors should not be able to
generate a false 10GbE end of frame. For the word-striped version, this
requirement can be met by constructing the word following the word with the
"End of Packet" character (T) in a way so it cannot be generated from data
by 3 or fewer errors. This can be accomplished by using 2 non-data
characters plus at least one disparity dependent 6B or 4B vector. The only
question is whether the result should also serve as a normal repetitive
Idle word. So in the worst case, we might be saddled with an initial Idle
different from the following ones, which is no worse than the initial KKKK
column for column-striping.

We have previously made clear that the suggested formatting changes are
optional and not prompted by word-striping requirements at all. If one
simply reverses the transmission order of bytes from 0,1,2,3 to 3,2,1,0 one
can gain some advantages. Outside of Hari, this change would not be visible
so it is not fair to describe it as "convoluted" if you stick to the
dictionary definition of this word. Such an advance obviously can only be
developed in a cooperative climate and so we drop it.

You state "Column-Striping as proposed is extendable (sic) to any number of
lanes with no protocol changes". How about 5 lanes? Could your out of hand
dismissal of 5 lanes have anything to do with its incompatibility with your
current proposal? An extension of column-striping with no changes to lets
say 8 lanes would clearly increase the minimum IPG and the granularity of
skip insertions and removals. So you are faced with the choice of accepting
these undesirable side effects or to make some changes in  operating mode.
In contrast, a different number of lanes with word-striping just entails a
trivial change in the multiplexers. The size of the IPG and the granularity
of the skip function are invariant.

You claim again, with more emphasis and detail, a power advantage in the
CDR and SerDes area and refer to implementations that "are sensitive
(proprietary?) in nature". This claim is hard to accept since word-striping
is functionally significantly less demanding in this area, because there is
no need for bit alignment and byte comparisons among the several lanes. If
you have a good low power technique applicable to column-striping, there
would be absolutely no reason not to use it for word-striping as well if it
is indeed superior to a design tailored specifically just for the word
striping requirements. A well designed front-end benefits both versions
equally.  Since the column-striped approach requires greater design skills,
the identical designers will surely be able to develop low power front-ends
for the word-striped version as well. Such design differences have really
nothing to do with the intrinsic merits of either word-striping or

I have the impression that you see yourself as the impartial arbiter for
the issues at hand. That is always a very tough and demanding role. In
several notes, you stated that you are a very busy man. I carefully study
all your relevant notes and here and there, I find clues that perhaps you
did not have enough time to study the details of word-striping and all its
ramifications. I also think you did not apply the same kind of ingenuity in
thinking about word-striped implementations as you did for column-striping.
So I am surprised at the level confidence with which you assert your

I would like to end on a positive note of agreement  with one of your
statements. In a note to a correspondent, entitled  Re: Feliz Haridad,
dated Wed, 22 Dec 1999 11:36:29 -0500 (EST)  you wrote: "You really need to
review proposals before you comment on them". That is sound advice and I
would amplify it to "review very thoroughly ".

Best regards,

Albert Widmer     Phone: 914 945-2047       Email: widmer@xxxxxxxxxx
IBM T.J. Watson Research Center
Yorktown Heights, NY 10598-0218