Re: PAM-5 at 5 Gbaud
Thank you for raising these issues. We are fully aware of their
relevance and we plan to give a detailed presentation at the March
plenary addressing them.
Thank you again for your interest
Oscar E. Agazzi
16215 Alton Parkway
Irvine, CA 92618
Tel (949) 450-8700
> I have some question marks regarding your presentation in Dallas:
> "10 Gb/s PMD using PAM-5 modulation"
> by Oscar Agazzi
> a) 5 GHz equalizer
> You use in your simulations a Decision Feedback Equalizer (DFE) at 5 GHz. You
> mention, to support your proposal, that DFEs are also used in Fast Ethernet
> and 1000BASE-T. However, the latter DFEs run at 125 MHz (8 nsec baud period).
> The DFE that you are proposing must run 40 times faster (200 psec baud
> A DFE has a feedback loop (slide # 15 in your presentation) that consists of
> at least one adder, a 5-level slicer and the internal delay of one flip-flop.
> The serial operations in this feedback loop (addition + slicer + internal
> delay of the flip-flop) have to be completed within one baud period, in this
> case 200 psec.
> There was a very heated debate within the 1000BASE-T Task Force two years ago
> whether the DFE could be implemented at 125 MHz. I remember that during these
> debates you and Broadcom vehemently sustained that it would be extremely
> difficult to implement the feedback loop in 8 nsec. Now you propose to
> implement it in 200 psec.
> I have doubts whether this DFE could be moved from the world of simulations
> into a real implemented system. And in CMOS, as slide # 2 of your
> presentation seems to suggest. Even using parallel processing.
> For comparison, the architecture I proposed, PAM-5 4-WDM at
> 1.25 Gbaud, using the 1000BASE-T PCS, (see my presentations
> in Kauai and Dallas) has two options:
> 1) Viterbi decoding, with 6 db coding gain
> 2) symbol-by-symbol decoding, with 3 db coding gain
> There is already a significant amount of previous work
> on fast parallel processing of Viterbi decoders that can
> be found in the open literature. See, for example, Ref. 5
> in my presentation in Kauai:
> H. David, G. Fettweis and H. Meyr
> "A CMOS IC for Gb/s Viterbi decoding: System design
> and VLSI implementation"
> IEEE Trans on VLSI Systems, vol 4, pp 17-31, March 96
> Specifically, following the detailed guidelines of this Ref,
> the complete Viterbi decoder can be implemented using a
> 312.5 MHz clock (3.2 nsec clock period). This is also a very
> handy clock, since we need it anyway in the parallel interface.
> These 3.2 nsec are enough to implement the path metrics
> update, which is the bottleneck in fast Viterbi decoders.
> However, I also suggested to you that we could propose
> in the 10 GbE Task Force to use the 3-dB coding option
> of this PCS, if you prefer. The 3-dB coding option does not
> use Viterbi decoding.
> The burdens on the receiver analog front end of your proposal are even more
> b) 5 GHz ADC
> The main claim of your proposal is that it can reach 500 meters of installed
> multimode fiber (500 MHz*km bandwidth)
> At 5 Gbaud and 1300 nm wavelength the optical eye pattern of PAM-5 is
> completely closed even before reaching the 200 meters link length.
> At 500 meters the ISI (Inter Symbol Interference) is as bad or worse than the
> ISI we get in Fast Ethernet using 100 meters of cat-5 Copper wire. In Fast
> Ethernet we needed a true 6-bit (64 levels) ADC for the DFE to be able to
> deal with this strong ISI.
> Slice # 15 of your presentation shows an ADC.
> I think that you will have to use at least a 6-bit ADC in your system. This
> also looks extremely difficult to implement at 5 GHz. For example, in the
> last International Solid-State Circuits Conference held this month in San
> Francisco, the maximum sampling rate achieved by a nominal 6-bit CMOS ADC was
> 800 Msamples/s (only 5-bit effective using a 200 MHz signal). It was
> fabricated in a 0.25 um process.
> For comparison, PAM-5 4-WDM at 1.25 Gbaud does not have
> any ISI up to 400 meters and uses an 18 level "soft slicer".
> This is barely a 4-bit ADC. And it is sampled at 1.25 Gbaud.
> All the simulations I presented in Kauai were obtained using
> this simple 18-level ADC. And, as I showed in Part IV of the
> presentation, 18 levels are enough to reach an actual coding
> gain close enough to the ideal.
> This should not come as a surprise. It is a well known fact
> that Viterbi decoders for binary encoded information (PAM-2)
> need very simple "soft-slicers" to get most of the coding
> gain of the convolutional code. A "soft-slicer" for PAM-2
> coding needs only 8 levels to get a performance near to the
> ideal Viterbi decoder. See, for example:
> J. A. Heller and I. M. Jacobs
> "Viterbi decoding for satellite and space communications"
> IEEE Trans on Commun Tech, vol COM-19, pp 835-848,
> October 1971
> S. B. Wicker
> "Error control systems for digital communications and
> Prentice Hall, 1995
> (A "hard-slicer" is the standard n-level slicer for PAM-n.
> A "soft-slicer" uses more intermediate levels to get more
> accurate decisions).
> c) Dynamic range of the Receiver Analog Front End
> You will need 5 Gbaud Transimpedance Amplifiers (TIA) and AGCs (slice # 15 of
> your presentation). What should be the needed dynamic range of these blocks ?
> A 6-bit ADC means about 36 dB dynamic range:
> 20*log(64) = 36 dB
> However, you would need to add some margin in your design of the analog front
> end. This means, you will need TIAs and AGC at 5 Gbaud with a dynamic range
> of about 41-46 dB. This also looks extremely adventurous to propose in CMOS
> (and I would add, in any technology).
> On the other hand, using PAM-5 at 1.25 Gbaud, and
> remembering that:
> 20*log(18) = 25 dB
> we will need TIAs and AGCs at 1.25 Gbaud with a
> dynamic range of only 30-35 dB.
> All the above place an interrogation mark on the technical viability of the
> serial PAM-5 approach at 5 Gbaud.
> I doubt if the HSSG members were aware of these technicalities when they
> rushed to a strawpoll in Dallas, specially since you did not post your
> presentation in the web site before the Dallas meeting for a peer preview.
> This did not give the HSSG members a fair chance to take a critical look at
> your proposal.
> Jaime E. Kardontchik
> Micro Linear
> San Jose, CA 95131
> email: kardontchik.jaime@xxxxxxxxxxx