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Re: 64/66 control code mapping





Rich

Rich Taborek wrote:
> 
> In the case that the PCS is 64B/66B in support of a Serial PHY type, I see no
> requirement for 8B/10B encoding/decoding to be performed. The fact that both the
> XGMII and 64B/66B support special codes to simplify synchronization,
> delineation, error checking, parallel lane deskew, jitter control, clock
> tolerance compensation, etc. and that these codes are similar to those used by
> 8B/10B are a credit to the elegant and timeless nature of the 8B/10B
> transmission code developed by Widmer, et. al.
> 

It sounds like you're laying it on a little thick with
"the elegant and timeless nature of the 8b10b"! Though I
agree that this encoding has enjoyed much success, and
deservedly so, I don't believe this accounts for any need
of "parallel lane deskew, jitter control, clock tolerance
compensation, etc" codes in 64b/66b. This encoding has no
inherent parallel features which need to be deskewed and
I can't see how any special codes can be used for jitter
control or clock tolerance.

Please enlighten the less fortunate ;^)

Ben

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