Re: Specific PMD support of XAUI/XGXS
Rich Taborek wrote:
> Are you saying that your PAM5/4WDM proposal will not be compatible with
> XAUI/XGXS? Please clarify.
> Best Regards,
Please, do not put in my mouth things that I did not say.
I repeat below what I said before and I leave to others
to fight the XAUI/XGXS/etc wars:
> I am very open and flexible with respect to supporting /A/,/K/, etc..
> However, I would like to point out that these are completely
> unnecessary in my proposal "PAM-5 4-WDM at 1.25 Gbaud".
Jaime E. Kardontchik
San Jose, CA 95131
> Jaime Kardontchik wrote:
> > Rich Taborek wrote on Friday 00:26, March 17:
> > >
> > > .............. A WWDM or Parallel Optics PMD
> > > requires its PCS to support /A/, /K/, and /R/ to perform synchronization,
> > > deskew, alignment and clock tolerance compensation. This information
> > > must indeed be transported out through the PMD to enable the remote
> > > PCS receiver to perform all of the latter functions.
> > Rich,
> > I am very open and flexible with respect to supporting /A/,/K/, etc..
> > However, I would like to point out that these are completely
> > unnecessary in my proposal "PAM-5 4-WDM at 1.25 Gbaud".
> > I do follow exactly the same synchronization steps that you
> > mention in Albuquerque's presentation, slide # 15:
> > "4-lane link synchronization is a 5 step process
> > 1-4 acquire sync on all 4 lanes individually
> > 5 align/deskew synchronized lanes "
> > Since I use the 1000BASE-T PCS instead of the 1000BASE-X
> > PCS (8b/10b), the only difference is that each lane has its
> > own 1000BASE-T PCS clocked at 312.5 MHz (instead of the
> > 8b/10b coder) and a SERDES clocked at 1.25 GHz (instead
> > of 3.125 GHz).
> > The SERDES takes the four PAM-5 symbols generated by
> > the 1000BASE-T PCS every 312.5 MHz clock cycle and
> > delivers them serially to the PMD. Byte sync at the receiver
> > is performed using the IDLE properties of the 1000BASE-T
> > PCS. Lane alignment is trivial once you performed byte
> > sync on the individual lanes.
> > Jaime
> > Jaime E. Kardontchik
> > Micro Linear
> > San Jose, CA 95131
> > email: kardontchik.jaime@xxxxxxxxxxx
> Richard Taborek Sr. Phone: 408-845-6102
> Chief Technology Officer Cell: 408-832-3957
> nSerial Corporation Fax: 408-845-6114
> 2500-5 Augustine Dr. mailto:rtaborek@xxxxxxxxxxx
> Santa Clara, CA 95054 http://www.nSerial.com