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Re: 16-bit 625Mbaud XGMII

Andreas Bechtolsheim wrote:

> Jaimie: you need to count package pins, not signal I/Os.
> Your 625 MHz XGMII using LVDS differential signalling
> requires 76 pins, which is the same pincost as the
> 312.5 MHz XGMII using single-ended drivers.
> In addition, you would need to run at least part of
> your logic at the 625 MHz which is significantly
> more difficult to implement than staying with a
> clock frequency of 312.5 MHz.

Yes. I noticed that I did not use a consistent system.
Also the 4 lanes after the PMA are differential, i.e.,
they mean 8 pins.

The logic at 625 MHz is really very simple, the number
of gates is very small and you only need it at the interface.
 For instance, you enter the PCS/PMA chip with
16-bits at 625 Mbaud and immediately you do a
serial-to-parallel conversion to end with a
32-bit at 312.5 Mbaud. From then on, you continue
in the same way as H. Frazier showed in his
Nov 99 presentation "10Gig MII update".
You already have this type of logic and at much
higher speed in the various proposed SERDES,
where it runs even at 3.125 GHz in CMOS.

I think that specifying a 16-bit LVDS XGMII
will be consistent with the trend towards unifying the
LAN and WAN PHYs. The WAN PHY already uses
16-bit LVDS at ~ 625 Mbaud. See, for instance,
P. A. Bottorf et al presentation "A unified PMD interface
for 10 GbE", March 2000. This 16-bit LVDS is an
exposed interface.

Finally, I think that the XGMII should be the only
specified interface. The XAUI interface creates a
compatibility and interoperability issue, since its
outputs are coded symbols and everyone wants
to use a different coding. Unless, the XAUI is defined
as a simple "extender", with the XGMII interface
both at its input and output. But this is not what
the XAUI proponents want.


Jaime E. Kardontchik
Micro Linear
San Jose, CA 95131