Re: 64/66 control code mapping
I'd like to make a couple comments on your note below:
Regarding horizontal eye opening, serdes jitter tolerance
is more a function of the PERCENTAGE eye opening rather
than the absolute amount in picoseconds. That is, the
uncertainty in the receiver's strobe placement is a function
of the eye closure -- the distribution of edge placements
it is trying to align to. Looking at your analysis below,
the 'Eyedelta%' (percentage of the bit) width is virtually
identical for the scrambled and 8b/10b encodings in each case.
(What is most likely going on is that the advantage due to the
lower frequency content of the scrambled data stream is offset
by the longer run lengths.)
What isn't shown (and can't be) in those eye diagrams is the
relative difficulty of the receiver's job. Run lengths are
a huge factor here. Analyses from several sources support
run lengths as a big consideration in defining worst case
jitter tolerance patterns.
Second, I want to take exception to your statement: "Once we
reach the long PCB trace, it is clear that 8b/10b has fallen
off of a cliff." The 60% eye opening shown is well within
receiver capabilities. Specifications require them to work
down to 30 or 35% eye opening. Also, the presentation,
shows hardware results for virtually the same physical case.
The eye after 20 inches is beautifully open due some simple
pre-emphasis. I just don't see the cliff (at least, nowhere
I'm not arguing against any aspect of 64/66 code here. My
only point is that serial data transmission with 8b/10b code
is a well-developed technique in the toolbox of a large and
growing number of vendors. In my opinion it is a low-risk
plan for moving 3+ Gb/s across 20-something inches of PCB.
Rick Walker wrote:
> Dear Rich,
> > Rich Taborek <rtaborek@xxxxxxxxxxx> writes
> > I realized yesterday while analyzing SLP as a XAUI code that your
> > Albuquerque presentation of PCB trace analysis of 8B/10B @ 3.125 Gbaud
> > vs. scrambles @ 2.5 Gbaud shows better eyes for 8B/10B than
> > scrambling for 5 out of 6 cases.
> > Ignoring all slides at >3.125 Gbaud since they are not relevant to
> > XAUI trace s, the 8B/10B eye is superior to the slower scrambled eye
> > in:
> I don't agree. You've picked a very biased definition of "superior".
> Usually an eye margin is defined in terms of both time and voltage. You
> seem to be focussing solely on voltage and completely disregarding the
> time axis.
> Lets look at each slide:
> slide EyedeltaT EyedeltaV Description
> ----- -------- --------- -----------
> 15 295ps 355mV DC 8b/10b 3.125G test setup
> 14 373ps 347mV DC scrambled 2.5G test setup
> 10 297ps 355mV AC 8b/10b 3.125G test setup
> 9 372ps 311mV AC scrambled 2.5G test setup
> 28 367ps 313mV DC scrambled 2.5G 5.5" diff pair
> 29 281ps 315mV DC 8b/10b 3.125G 5.5" diff pair
> 20 289ps 311mV AC 8b/10b 3.125G 5.5" diff pair
> 19 359ps 279mV AC scrambled 2.5G 5.5" diff pair
> 25 278ps 321mV AC 8b/10b 3.125G 11" diff pair + 2 via
> 24 344ps 311mV AC scrambled 2.5G 11" diff pair + 2 via
> 27 191ps 165mV AC 8b/10b 3.125G 22" diff pair + 4 via
> 26 242ps 203mV AC scrambled 2.5G 22" diff pair + 4 via
> > The only slides which show the scrambled eye to be superior is for the
> > case of a 22" differential pair and 4 vias in slides 26,27,33.
> My reading is that the scrambled code is superior in the time opening
> for ALL the cases and has superior voltage margin in the worst case
> In the voltage axis, both codes have quite useable eye openings until
> the worst-case interconnect. Once we reach the long PCB trace, it is
> clear that 8b/10b has fallen off of a cliff.
> So, I get a completely opposite reading from the data, Rich. Scrambling
> is only slightly degraded in the voltage axis due to BLW - and this is
> for the short distance traces. For electrical links, there is no large
> gaussian noise term, so openings bigger than ~50mV generally have
> unmeasurable BER. By this reasoning, both codes show extremely wide
> voltage margins.
> You can see that the difference is only due to capacitive coupling by
> comparing slides 20/19 with 28/28. In the latter case, when the links
> are DC-coupled, there is only a trival 2mV difference between the two
> The presentation doesn't say what the AC coupling frequency was. The
> BLW penalty can be reduced to zero if two chips are DC coupled on the
> PCB. It can also be reduced arbitrarily by increasing the capacitor
> > In a nutshell, the "eye" analysis seems to be either inconclusive or
> > questionable since 8B/10B seems to "fall off a cliff" with respect to
> > scrambling somewhere between 11"/2 vias and 22"/4 vias. Where is the
> > cliff and what accounts for it? This is why I'm having great
> > difficulty with your suggestion to "slow down XAUI a bit".
> The cliff is can be explained by noting that a PCB interconnect has an
> impulse response with a certain half-width in time. When the bit time
> is larger than the impulse response width, you see essentially no
> amplitude degradation at the mid-eye.
> Once the bit time gets shorter than the channel impulse response width,
> 010, or 101 patterns will have reduced amplitude.
> Because 8b/10b has a narrower eye it will hit this "wall" 25% earlier
> than a scrambled code. This is certainly the effect in slide 27 as
> can be seen by the distinctive "double trace" in the eye diagram. The
> inner of the two traces is caused by the reduced amplitude of the 010 and
> 101 data patterns.
> So, my conclusion is that this data clearly shows that scrambling
> provides a considerable margin improvement for the worst-case link, and
> has negligable penalty for short links.
> As I said in Kauai, I think it would be an improvement to replace 8b/10b
> with a higher efficiency code. However, it is not yet clear whether it
> is worth the pain. To help us determine that, we need to keep our eyes
> and ears open and let the group dispassionately evaluate the pros and
> cons of the various options. It will certainly be painful to consider
> dropping our old friend: 8b/10b.
> My belief is that ~4-5 Gb/s is near the ultimate skin-loss limit for 0.5
> Meter NRZ signalling with 4 mil differential copper traces. You can
> push this by equalizing, reducing trace length, or by reducing layout
> density by widening the traces.
> It is not clear whether 3.125G is pushing too aggressively for low cost
> implementations. For this we will have to trust the experience and
> experimentation of the various 10GbE participants over the next few
> Best regards,
> Rick Walker
Mike Jenkins Phone: 408.433.7901 _____
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