Re: Single ended XGMII
I am doubtfull if the rise and fall time will be anywhere close to (say <
20%) of period
at 4mA drive even for small trace lengths. I guess it has to be 8 or 16 mA.
I had to use
16 mA at 125 MHz (10 bit interface).
At 08:41 AM 3/24/00 -0800, you wrote:
>Curt and all,
>Could I suggest to reduce the driving capability of the
>output buffers to 4 mA for data and control lines (36 lines
>total) and keep 8 mA only for the recovered clock ? I used it
>the past for Fiber Channel chips and it was very effective.
>Essentially, it reduces the switching noise by half.
>Curt Berg wrote:
> > A few comments on using a single ended XGMII:
> > - Today we have several Quad SERDES chips in production, operating
> > at 1.25/2.5 Gbit/s with 8B or 10B interfaces. Most
> > use a 3.3V I/O swing, and I would guess about 40 ohm (nominal)
> > LVTTL/LVCMOS drivers. This effectively is a 32 bit interface.
> > I would say, these devices seem to function well for many companies.
> > - Some vendors are event moving to higher integration then
> > Quads, still using single ended interface. This further indicates
> > that noise is not a major problem.
> > - Single ended interface on the MAC side is not an issue. There
> > are many ASIC in production today with 400+ single ended I/Os,
> > and board with several tens of thousands of single ended nets.
> > - If we for XGMII use a (1.5 V swing) HSTL instead, and
> > move to a 50-55 ohm impedance controlled driver, we should be
> > able reduce the effective noise levels by close to a factor
> > of three.
> > My conclusion is that the industry keeps pushing the
> > capabilities of single ended interfaces, just because
> > differential interfaces double this pincount.
> > If we can reduce the noise by a factor of 3, and not
> > move up much in frequency, from existing proven solutions,
> > I believe we have a workable solution.
> > -Curt Berg-