Re: 16-bit 625Mbaud XGMII
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> Date: Tue, 28 Mar 2000 09:59:59 -0800
> To: Andreas Bechtolsheim <avb@xxxxxxxxx>, stds-802-3-hssg@xxxxxxxx,
> From: JR Rivers <jrrivers@xxxxxxxxx>
> Subject: Re: 16-bit 625Mbaud XGMII
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> How about 1.25 Gbaud LVDS?
Operating at 1.25 Gbaud LVDS and source synchronous would require deskew as your
bit period is only 800 ps. Also differential signal have the inherent with in
the pair skew. Most differential signal are often routed as two single ended in
any complex board.
I would be comfortable with 612.5 Mb/s single ended with HSTL like levels. In
the case of single ended the I/O pin are equal to differential at 1.25 Gb/s. You
would need to add additional ground/power pins for single ended ~25%.
Here is an example:
Differential GssGssGssGssG 4*1.25 = 5Gb/s
Single Ended GsGsGsGsGsGsG 6*0.6125= 3.75 Gb/s
But your data rate is half as high with bit period of 1.6 ns, which allow for
source synchronous transmission!
> At 03:07 PM 3/20/00 -0800, Andreas Bechtolsheim wrote:
> >Jaimie: you need to count package pins, not signal I/Os.
> >Your 625 MHz XGMII using LVDS differential signalling
> >requires 76 pins, which is the same pincost as the
> >312.5 MHz XGMII using single-ended drivers.
> >In addition, you would need to run at least part of
> >your logic at the 625 MHz which is significantly
> >more difficult to implement than staying with a
> >clock frequency of 312.5 MHz.