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re: serdes design vs run length

Joel and reflector,

The main relationship beween coding (max run lenth) and SERDES is related to the loop bandwidth of the CDR.  The LBW is set with a loop filter.  Some of us SONET oriented folks like this to be external, where we can have a nice low LBW with good damping.  Many (all?) GE type SERDES use on chip loop filters.  This makes for small on chip capacitors, higher LBW, and more peaking (maybe).

So, is it cheaper to build a capacitor in ceramic, or on a die?  pf for pf, caps are cheaper as chip caps, not integrated on the die.  Which is lower cost?  Once we are in these type of tradeoffs, it can safely be said that this is a local optimization issue of second order importance.  

What also drives die size is the VCO type.  Reactance based VCOs are larger, but ring oscillator VCOs have higher phase noise.  But, this is an implementation issue.  The link should set the jitter (phase noise) specs and the SERDES guys can fight it out.

So, I don't see that 64b66b vs. SONET type scrambling has any impact on the SERDES.  Both run at about 10G, and have similar LBW needs.  (others can debate the 2.5G / 3.125G topics).

The primary thing that will drive SERDES die size is I/O count. But the I/O to the SERDES from an intermediate XAUI or XGMII to SERDES interface CMOS device is not an interface that is 'on the table' as a standardized interface.  Right now the defacto standard is the OIF style x16 interface.  Can CMOS support a x4 clocked interface at ~2.5GHz?  Your thoughts are appreciated.

Regards, Bill

Bill Woodruff				ph: 805 496-7181 x14
GiGA North America Inc.		fax: 805 496-7507
299 W. Hillcrest Dr., Suite 106		woodruff@xxxxxxxxxxx
Thousand Oaks, CA  91360

  >>  Howdy all,

  >>  I was looking through some notes from Albuquerque and came across some
  >>  remarks I have heard and wanted to bring it up on the reflector.

  >>  I had heard some folk pointing out that there are some of us worried
  >>  about the relative board costs, relative emi costs, relative systems
  >>  cost, but ignoring relative costs directed at the serdes.  So, to remedy
  >>  this, let me ask the following to those of you whom design serdes
  >>  devices:

  >>  What impact does the encoding or run length have on the relative cost of
  >>  a serdes device at 2.5gigabit and 3.125gigabit for 8b10b, Scrambled, and
  >>  64b66b?  Does the extended run length really drive the cost, or have we
  >>  just not employed new methods into phase lock control that might reduce
  >>  the run length impact?

  >>  Or are there other serdes issues that one coding scheme has over the
  >>  other that impact relative cost more?

  >>  Thanks and take care
  >>  Joel Goergen