Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

RE: serdes design vs run length

Mike, and all:

Everyone is contributing good analysis to the excessive run length of the
scrambled code comparing to the 8B/10B which is 5 bit maximum.  In addition
to those issues presented, the circuit will need as high loop-gain as
possible to minimize error signal voltage drifting.

However, there will be an excessive DJ caused by long run length immutably
followed by 10110.. of the smallest pulse width.  There is no cure for it.
Even if COST is no objection.


Edward S. Chang
NetWorth Technologies, Inc.
Tel: (610)292-2870
Fax: (610)292-2872

-----Original Message-----
From: owner-stds-802-3-hssg@xxxxxxxx
[mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Mike Jenkins
Sent: Sunday, April 02, 2000 5:13 PM
Subject: Re: serdes design vs run length


This is in response to your run length question a couple days ago.
Bill Woodruff did a good job describing the PLL design tradeoffs.
I could add a few technical comments (e.g., the need for larger
valued DC blocking caps with good high frequency response, and
the implicit minimum BW requirement to track low-frequency wander
below several hundred kHz), but I don't think that's the main issue.

My connection here is integrated CMOS serdes, so that's where this
response is coming from.  If "cost" means unit cost of a product
still to be developed, then I don't have much to say.  The cost
I would worry about is development-related -- costs of bringing
such a product to market -- technical risks which translate into
schedule risks and, therefore, into missed market opportunities.

To my (admittedly limited) knowledge, most existing 1-3G serdes
assume 8b10b code.  And they owe their existence to a long process
of solving non-trivial design issues.  To my (admittedly biased)
mind, an existing, proven solution counts for more than a few
comparison points against a concept that may or may not have some
small, theoretical technical advantage.


Joel Goergen wrote:
> Howdy all,
> I was looking through some notes from Albuquerque and came across some
> remarks I have heard and wanted to bring it up on the reflector.
> I had heard some folk pointing out that there are some of us worried
> about the relative board costs, relative emi costs, relative systems
> cost, but ignoring relative costs directed at the serdes.  So, to remedy
> this, let me ask the following to those of you whom design serdes
> devices:
> What impact does the encoding or run length have on the relative cost of
> a serdes device at 2.5gigabit and 3.125gigabit for 8b10b, Scrambled, and
> 64b66b?  Does the extended run length really drive the cost, or have we
> just not employed new methods into phase lock control that might reduce
> the run length impact?
> Or are there other serdes issues that one coding scheme has over the
> other that impact relative cost more?
> Thanks and take care
> Joel Goergen

 Mike Jenkins               Phone: 408.433.7901            _____
 LSI Logic Corp, ms/G715      Fax: 408.433.7461        LSI|LOGIC| (R)
 1525 McCarthy Blvd.       mailto:Jenkins@xxxxxxxx        |     |
 Milpitas, CA  95035      |_____|