Re: PAM-5, what are your BERs ?
JR Rivers wrote:
> During the course of these discussions, I've seen people use "hard to do in
> CMOS" as a reason to reject a proposal.
> I'm not trying to say that someone couldn't/shouldn't build a 10GbE
> transceiver in CMOS; however, I am questioning the REQUIREMENT that it be
> built in CMOS at standardization. I've been working on Ethernet products
> for quite a long time, and every signalling technology has started off with
> some non-CMOS implementation and eventually been reduced to CMOS.
There is no such requirement.
However, there are several proposals on the table (not only
PAM-5 proposals) that claim that they can implement their
transceiver in CMOS. An example, is 8b/10 4-WDM at
3.125 Gbaud. Another example, is Oscar Agazzi's claim that
he can implement his "PAM-5 serial at 5 Gbaud" transceiver
in low cost CMOS. (I am quoting one of his slides in his
presentation) These proposals are included in spreadsheets
and submitted to strawpolls.
These claims are made to point out a significant advantage
over other proposals that would seem to need more expensive
and less accesible technologies.
We should take these claims seriously as intended to say
that their authors believe that their transceivers can be
implemented NOW using CMOS.
In some far future, of course, we can all claim that all the
proposals will be implemented in low cost CMOS ...
Jaime E. Kardontchik
San Jose, CA 95131