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Re: serdes design vs run length


Here's a brief reply from Mr. Steve Dreyer of nSerial on the subject of CDR
design which I hope will help answer some questions for you:

The "smart" way to design the CDR is to always check the input
in every bit interval for a transition.   If there is a transition,
compare it's phase to the feedback clock and pass the phase error to
the charge pump.  If there is no transition, don't pass any
phase error to the charge pump, and the PLL just keeps running
at the frequency it is tuned to.  If you assume that the charge pump
leakage is zero, the PLL can survive an infinite run length.
In real life, the run length is limited to many tens of
bits by the real charge pump leakage.  This technique requires
some complicated logic around the PLL and phase detector,
it is nontrivial.   So, it really doesn't matter from a CDR
standpoint to us what coding/scrambling is used, as long as
there is some transitions in a reasonable number of clock
cycles (at least one transition every 10 bits would be a
conservative guideline).


Best Regards,

Joel Goergen wrote:
> Howdy all,
> I was looking through some notes from Albuquerque and came across some
> remarks I have heard and wanted to bring it up on the reflector.
> I had heard some folk pointing out that there are some of us worried
> about the relative board costs, relative emi costs, relative systems
> cost, but ignoring relative costs directed at the serdes.  So, to remedy
> this, let me ask the following to those of you whom design serdes
> devices:
> What impact does the encoding or run length have on the relative cost of
> a serdes device at 2.5gigabit and 3.125gigabit for 8b10b, Scrambled, and
> 64b66b?  Does the extended run length really drive the cost, or have we
> just not employed new methods into phase lock control that might reduce
> the run length impact?
> Or are there other serdes issues that one coding scheme has over the
> other that impact relative cost more?
> Thanks and take care
> Joel Goergen
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