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Re: Interface reality check


I will let the "chip" people give more information on the gate complexity
issues.  I have not been directly involved in chip design for years.

One of the reasons that I decided to support the Nortel proposal, that I
refer to as "frame stuffing", is that it does NOT use HDLC like byte
stuffing.  It uses known fixed "frames" to delineate active data, similar to
ATM which IS reliable and predictable.

Thank you,
Roy Bynum

----- Original Message -----
From: Rick Walker <walker@xxxxxxxxxxxxxxxxx>
To: Roy Bynum <rabynum@xxxxxxxxxxxxxx>
Cc: <stds-802-3-hssg@xxxxxxxx>
Sent: Wednesday, April 12, 2000 7:10 PM
Subject: Re: Interface reality check

> Hi Roy,
> > Thank you for your efforts.  I still don't see why the WAN compatible
> > should be burdened with all of these add on complexities, in addition to
> > additional ~3% of bandwidth loss.
> I suppose that the reason, from the viewpoint of those who support this
> option, is that the modest work to implement the "gearbox" is tiny
> compared to the complexity of a complete SONET framer and HDLC FCS
> mechanism.
> In addition, the WAN portion of the Uni-Phy proposal leverages any work
> done on 64b/66b for the LAN by simply adding a SONET-like wrapper.
> My perception is that the "extra burden" is likely to be very much less
> than the alternative full SONET framing mechanism.  If we didn't think
> this, we wouldn't have made the proposal.  We are not masochists.
> However, I understand that you may see it differently.  I am not a SONET
> expert and have not seen a gate count of a SONET-style framer with
> modifications for 10Gb Ethernet support.  I am simply daunted by the
> exceedingly complex description and block diagram.
> If you want to convince a larger audience, I'd recommend that you
> consider doing a design, or finding some information on an existing
> design, and posting the comparative implementation data.  I have already
> done so for a 64b/66b codec design at the last meeting.
> Best regards,
> --
> Rick Walker