Re: XAUI IO specs
Since I am an electrical PHY guy, I have been lurking and waiting for the
I/O subject to surface. It may be premature to talk about I/Os when the
overall solutions have not been nailed down yet, but since the subject has
been raised, I will offer clarification of the I/O issue at hand.
an excerpt from Rich's reply,
>When the Output is set to a logic one, the positive differential signal,
>referenced to a 0 V ground, is a maximum of +400 mV and the negtive
>signal, referenced to a 0 V ground, is a maximum of -400 mV.
>When the Output is set to a logic zero, the positive differential signal,
>referenced to a 0 V ground, is a maximum of -400 mV and the negtive
>signal, referenced to a 0 V ground, is a maximum of +400 mV.
>I'd call this V diff peak-to-peak, but this I'm NOT an expert in this
The above attempt at clarification made me more confused. No offense
intended, Rich. :) The way the above is worded I can still take it two
ways. I think if I look at the way each signal is described above, and in
the logic one case positive output is +400 from the common mode, and the
negative output is -400 from the common mode, then we have an 800 mV
differential for logic one, and also folowing the next paragraph we have
-800 mV leaving Vdiff =1600 mV peak-to-peak. I don't think this is the
case for several reasons.
Perhaps the numbers came from or match the IEEE LVDS spec on page 10 of
IEEE Std 1596.3-1996. The common mode is intended to be 1.2 Volts, and the
differential is NOT specified peak-to-peak, but merely differential. |Vd|
has absolute value signs around it and therefore doesn't care about
polarity. In this case, |Vd| max = 400mV. The picture has the output
driver at a common mode of 1.2 Volts, and each of 2 differential signals
swings single ended from 1.0 to 1.4 Volts. In one case the difference is
+400 mV (positive peak), and when polarity switches the difference is
-400mV (negative peak). The differential peak-to-peak then is +400 -
(-400) = 800 mV.
Differential I/O Specs can be confusing. Darn those factors of two!
Additionally, it is nice to know the common mode (average of the two
signals). If you truly mean LVDS, please reference IEEE Std, or
ANSI/TIA/EIA, or other LVDS compatible. Or, in the absence of referring to
a spec, draw a picture of the signal or write 1000 words.
I also realize that there are bigger fish to fry than I/O levels and it may
be premature to talk about I/O levels. However, if the XAUI/XGXS
solutions are maturing, please offer clear I/O definitions.
For happy reading, OIF (Optical Internetworking Forum) Document
#OIF99.102.5 has defined a common electrical interface between SONET framer
and serializer/deserializer parts for OC-192. It looks to be a fairly
mature document for what HSSG calls the PCS/PMA interface. This would be
the 16-bit serializer/deserializer and clock and data recovery spec. Some
work could be leveraged from this document.
Mixed Signal and VLSI Development
3605 Hwy 52 N
Dept. QXS Bldg. 050-2
Rochester, MN 55901
Internal E-mail: kdemsky@ibmusm07
External E-mail: kdemsky@xxxxxxxxxx
Rich Taborek <rtaborek@xxxxxxxxxxxxx> on 04/15/2000 05:05:52 PM
Please respond to rtaborek@xxxxxxxxxxx
To: HSSG <stds-802-3-hssg@xxxxxxxx>
Subject: Re: XAUI IO specs
I'll have to defer to Mr. Ali Ghiasi and Mr. Richard Dugan on this issue to
properly resolve the nomenclature. My understanding of the parameters
as follows using Vo Dif(max) 800 mV as an example:
When the Output is set to a logic one, the positive differential signal,
referenced to a 0 V ground, is a maximum of +400 mV and the negtive
signal, referenced to a 0 V ground, is a maximum of -400 mV.
When the Output is set to a logic zero, the positive differential signal,
referenced to a 0 V ground, is a maximum of -400 mV and the negtive
signal, referenced to a 0 V ground, is a maximum of +400 mV.
I'd call this V diff peak-to-peak, but this I'm NOT an expert in this area.
Mark Kerestes wrote:
> Rich, Ali
> On slide 22 of the XAUI/XGXS Proposal from Albuquerque was listed :
> Vo Dif(max) 800mV
> Vo Dif(min) 500mV
> Vin Dif(max) 1000mV
> Vin Dif(min) 175mV
> I assume these are truely Vdif and NOT Vdif peak to peak? I have some
> confusion from looking back at the
> Nov 5 1999 "HARI the Electrical Interface" which seems to have a table
> that mixes Vdif and Vdif peak to peak
> showing PECL vs LVDS vs HARI side by side.
> Best regards,
Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
nSerial Corporation Fax: 408-845-6114
2500-5 Augustine Dr. mailto:rtaborek@xxxxxxxxxxx
Santa Clara, CA 95054 http://www.nSerial.com