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Re: PMD discussion


The benefit of using existing components, testing, staffing, packaging at ~10
Gbps as opposed to 12.5 Gbps can not be overstated. As you say yourself
frequently: "There's no free lunch". The price of lunch is a bit more
complexity. However, this is an excellent tradeoff. 

64B/66B improves "time to market" by moving development from expensive, complex
and non-existant optics to relatively straightforward digital logic.

Since you are still pushing this tangent based on your latest response, I gather
that you believe that 64B/66B will INCREASE time to market for any PMDs that use
it. My sense is exactly the opposite. That is, using 8B/10B @ 12.5 Gbps instead
will increase time to market based on the "long pole" development of 12.5 Gbps
laser and other optoelectronic components, test equipment, etc. 

Best Regards,

Edward Chang wrote:
> Rich:
> Comparing to 8B/10b, which is a straight forward, repeatable, established
> code, 64b/66b is new, scrambling, staffing, dynamically adjusting, which is
> more complex than the 8B/10B.  Although, 64b/66b is able to maintain the
> data rate near 10 Gbps instead of 12.5 Gbps -- great advantage.  They are
> different in many ways.  The repeatable pattern is more easy to analyze,
> than the complex pattern.
> The 64b/66b is pretty much adopted in certain ways, that is not my point of
> discussion.  I do not have problem with that.  It is a fact, that 64b/66b is
> new, which is to be developed and tested, while 8B/10B is existing code,
> which has been proved in the field for long time.
> The reason this topic surfaced was the "time to release to market"
> discussion, not adaptation.
> Regards,
> Edward S. Chang
> NetWorth Technologies, Inc.
> EChang@xxxxxxxxxxxxxxxx
> Tel: (610)292-2870
> Fax: (610)292-2872
> -----Original Message-----
> From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> Sent: Friday, June 02, 2000 1:43 PM
> To: Edward Chang
> Subject: Re: PMD discussion
> Ed,
> I don't understand what you mean by your "key point" and how 64B/66B affects
> the PMD decision. If it's not 64B/66B, which is currently the ubiquitous PCS
> for all Serial PMDs, it would be another code. Based on this point alone,
> I suggest that you drop this tangent so that we may remain focused on how
> we're going to resolve the PMD issue.
> Scrambling is not an "unusual" technique. A simple scrambler is a linear
> feedback shift register (LFSR). The 64B/66B code is a very good compromise
> between a block code, such as 64B/66B and a pure scrambled code such at that
> widely deployed in all SONET links. Synchronization of a scrambled code is
> more complex and takes more buffering than for a block code. However, the
> added synchronization is neither "unusually" complex or expensive.
> A logic analyzer will easily be able to sync on the periodic 66B stream.
> The run length of the code is far longer than 8B/10B but limited (as opposed
> to pure scrambling).
> Mr. Rick Walker of Agilent and a plethora of coding and signaling experts
> have done an excellent job of proving the technical and economic feasibility
> of the 64B/66B code through numerous presentations to the HSSG and P802.3ae
> Task Force.
> I expect chips from vendors which employ 64B/66B to sample before year end.
> Pretty darn fast for such a complex code! You'll be surprised at the low
> power, low gate count and flexibility of devices implementing 64B/66B code.
> I'll conclude by stating that it is my personal opinion that 64B/66B is the
> best choice for a ~10 Gbps PCS for Serial PMDs.
> Best Regards,
> Rich
> --
> Edward Chang wrote:
> >
> > Chris:
> >
> > Probably for our focusing on PMD issue of 5-PMD or 3-PMD, our discussion
> of
> > serial vs. WDM will not help our course.  I will minimize our discussion;
> > however, I will re-state the key point.
> >
> > The new code 64b/66b is made to reduce the bit rate from 12.5 Gbps to
> > 10.3125, which is great.  However, nothing is free.  The bit rate
> reduction
> > is achieved at the expense of very unusual complex technique to achieve
> it.
> > Dynamically, continuously adjusting the data contents. To test, and
> analyze
> > the performance of a system is not an ordinary job.  The standard process
> of
> > using logic analyzer to analyze the logic waveform will be so dynamic from
> > one after another; as a result, one has to analyze the whole system of
> data
> > transfer and receiving to understand the significances of the waveform and
> > system performance, which is quite a new process.  Unless, you have
> > delivered a system before, you may not appreciate the complexity ahead.
> >
> > Regards,
> >
> > Edward S. Chang
> > NetWorth Technologies, Inc.
> > EChang@xxxxxxxxxxxxxxxx
> > Tel: (610)292-2870
> > Fax: (610)292-2872
> >
> > -----Original Message-----
> > From: owner-stds-802-3-hssg@xxxxxxxx
> > [mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Chris Simoneaux
> > Sent: Friday, June 02, 2000 3:03 AM
> > To: Edward Chang; Jack Jewell; 'Ken Herrity'; '802.3ae'
> > Subject: RE: PMD discussion
> >
> > Ed,
> >
> > If we are considering troubleshooting of serial vs WDM, we should also
> > consider how the optical link is troubleshooted (or troubleshot?).  This,
> as
> > far as I can tell, is a big unknown.  Especially as we are talking about
> > potentially multiple vendors with multiple ways of optically mux'ing and
> > demux'ing.
> >
> > Maybe someone can shed light on this.
> >
> > Chris
Richard Taborek Sr.                 Phone: 408-845-6102       
Chief Technology Officer             Cell: 408-832-3957
nSerial Corporation                   Fax: 408-845-6114
2500-5 Augustine Dr.        mailto:rtaborek@xxxxxxxxxxx
Santa Clara, CA 95054