questions on PCS synchronization
We've been taking a close look at the state diagrams in:
on pages 14, 16 & 17 and we've come up with some detailed questions.
1) In the synchronization state machine, the only way to become
is to wait for 64 continues frames with valid preambles and ensure that
BER is met (ie: <16 preamble errors in 125us). It has been mentioned
32/64 preamble error signal was intended for synchronization purposes,
and the hi_ber signal was meant to ensure a good BER. But, the diagram
shows that both kinds of errors will lead to the out of sync state (this
is ok - and a little redundant as only the BER signal would be needed).
The question is this: When a hi_ber causes loss of synchronization (but
there aren't 32/64 frames with invalid preambles) will the machine try
and sync up to a new position for the preambles?
2) In the TX state machine, shouldn't a requirement for leaving the
I (initialization) phase be that tx_tobe_decoded = Z? (otherwise a
non-error message would be transmitted when there would be an error)
3) The RX state machine in the Walker 64b/66b slide deck shows that
rx_err <= rx_EFRAME_G in the T (termination) phase. Shouldn't this read
rx_err <= rx_decoded so that if an error is found, the next phase (being
the error phase) will not send the MAC 2 error codes and no T code (even
though the T phase was valid) - but will send the T code followed by an
4) Also, in the RX state machine, should loss of sync require that you
go back to the I (initialization / sync) phase?
Thanks in advance,