Re: Gearbox reality check
Finally, someone is coming close to defining the "gear box", the piece of "magic" that everyone is referring to in order to make the
WIS work. Now, can you codify the amount of buffering required, and the flow differential alignments required to provide for the
total possible adjustment needed between the SONET framer and the 64B/66B PCS? For example, would 64k of multi-port memory as a
FIFO buffer, with asynchronous clocked registers on either side to provide for the bit and a robust memory manager provide the
required functionality? Is 64K enough. Is it more than what is needed? Are FIFO registers required? Is a memory manager needed,
and if so, what kind?
The reason that I ask this question is that in my years of experience with PoS, which uses a "gear box", it has proven to have a
massive lack reliability compared to 802.3 Ethernet. For example, the GbE transport error rate is about 3e-8 to 2e-10 errored
frames, depending on
the frame size. Compare this to the goal of only 3e10-2 dropped and errored packets over IP/PoS, and other services at 2e10-3 frame
ATM with a HEC frame structure has a much better reliability, 1e-8 to 1e-10 depending on the service. Is P802.3ae willing to take a
chance with a technology architecture that is associated with un-reliable data communications or would it rather use something that
is associated with reliable data communications? As a customer, it is very important for me to know.
----- Original Message -----
From: "Brown, Ben [BAY:NHBED:DS48]" <bebrown@xxxxxxxxxxxxxxxxxx>
To: "HSSG" <stds-802-3-hssg@xxxxxxxx>
Sent: Tuesday, June 20, 2000 1:39 PM
Subject: Re: Gearbox reality check
> Rich, Roy,
> It could be the terminology that is confusing the issue. I don't
> think the results are any different.
> The SONET frame is byte aligned.
> The OH content is bytes.
> The SPE content is 66-bit words when being filled or emptied
> at the WIS. Since the SPE is not an integral number of 66
> bits, the last word in 1 SPE will often "spill over" into
> the next SPE.
> The SPE content is considered bytes when being passed through
> the SONET network. When the SONET network needs to "adjust"
> 1 SPE with respect to another SPE in order to account for
> clock jitter and tolerances, it does so on byte boundaries.
> This could potentially further separate a 66-bit word. The
> SONET network also uses byte boundaries to find the OH bytes
> within a frame.
> The result is that the WIS is required to parse the SPE based
> on byte boundaries as indicated by the pointer logic (to find
> the start of the SPE) but the data it extracts is organized as
> 66-bit words, i.e. it only uses the byte boundaries to find the
> start and end of the SPE and to separate the OH bytes, while
> the content of the SPE is considered a collection of concatenated
> 66-bit words.
> How close is this?
> Rich Taborek wrote:
> > Roy,
> > This is the one of the tasks performed by the WIS. As I've explained, the SONET
> > OH is byte aligned and the data within the SPE is 66-bit aligned. Conversion at
> > each end is performed by the WIS.
> > Best Regards,
> > Rich
> > --
> > Roy Bynum wrote:
> > >
> > > Rich,
> > >
> > > A minor correction to one of your statements. In spite of the proposal to use a 66 aligned data stream in the WAN compatible
> > > the SPE remains byte aligned. There has to be some sort of, as yet undefined, "gear box" to stuff, re-time, and re-align the
> > > data stream into the byte aligned transmission signaling stream payload.
> > >
> > > Thank You,
> > > Roy Bynum
> > -------------------------------------------------------
> > Richard Taborek Sr. Phone: 408-845-6102
> > Chief Technology Officer Cell: 408-832-3957
> > nSerial Corporation Fax: 408-845-6114
> > 2500-5 Augustine Dr. mailto:rtaborek@xxxxxxxxxxx
> > Santa Clara, CA 95054 http://www.nSerial.com
> Benjamin Brown
> Router Products Division
> Nortel Networks
> 1 Bedford Farms,
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> Bedford, NH 03110
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