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RE: Gearbox reality check


If you're talking about the XGMII interface between the MAC-RS and
PCS (or MAC-RS and XGXS), this is currently defined as a 32-bit
data bus plus 4 bits control.  These pins are all dual data rate
(DDR) signalling at 156.25 MHz.


In message "Gearbox reality check", Ben Beeftink writes:

>Eric, Brad,
>I am not able to discuss about OIF/SUPI interface.
>What I have understand is that there is a technical limit for the
>electrical GMii MAC interface to produce a 1 channel in 10 Gbps.
>This because of decisions related to compactness silicon versus
>of operations.
>Do you agree that it is decided that GMII MAC will be 4 channels of 2.5
>Ben beeftink
>product manager Fiberoptics
>Kannegieter Electronica bv
>the Netherlands