Re: headless chicken
Regarding the Isolate bit in the MII Control register, I note
that when we originally specified this bit, its primary purpose
was to assist with the "hot insertion" of a PHY via the MII
When a 10/100 PHY is first plugged into an MII connector, it
comes up in the isolated state (electrically isolated from the
MII, with bit 0.10 set to 1). Once station management detects
the presence of a PHY at this connector, it can clear the Isolate
bit via MDIO/MDC.
In the original spec for the MII, we went to great lengths to
allow for the presence of two distinct PHYs below the MAC, with
the provision that only one PHY could be operable at a time.
We did this to allow for the case where you wanted to have one
PHY built onto your PCB (say a 10/100BASE-T PHY) and another
PHY accessible via the mechanical connector (say a 100BASE-FX,
10BASE5, or 100BASE-T4 PHY).
You could switch between the two PHYs by controlling the state
of the Isolate bit.
We didn't really intend it to support redundant PHYs, but I suppose
you could have made it work. As far as I can recall, 802.3 has
always left the concept of redundant PHYs up to implementers.
As I have said many times, I believe that the most important thing
we can do in 802.3ae is to specify a simple, reliable, and
interoperable Remote Fault indication. To me, this is a necessary
precursor for physical layer redundancy.
I continue to be concerned about the proposals for using LSS for this
function. I believe that LSS is several times more complicated than
what we need for this function, and that like the RF bit in
gigabit ethernet, we will wind up with a broken specification that
does not support interoperability.