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Re: ONLY one ref multiplier?: PMA clock reference


Nothing. RX_DATA, RX_CLK, TX_DATA and TX_CLK should do it. The rest should be
left up to the implementation.

Best Regards,

"Lysdal, Henning" wrote:
> Stuart, Justin, all
> I appologize if my answer to the fairly simple question by Justin:
> "Are there any that uses the 155MHz as a reference for OC192?"
> has confused some.
> My point was to show technical feasibility, so I'll give it a second try,
> and see if we can get the discussion back on track:
> Given the choice between a 155.52MHz reference clock and a 622.08 MHz
> reference clock most of the transceiver vendors (SerDes customers), I know,
> CHOOSE 155.52MHz.
> It might be easier to get good jitter performance with 622.08MHz
> (644.53MHz), but it is also more expensive.
> Maybe we should start discussing which parts of the OIF spec. should be
> copied for Ethernet rather than going over the details of which frequencies
> goes where. I guess we can all agree, we need RXDATA, RX_CLK, TX_DATA and
> TX_CLK. What else do we need to specify?
> Regards,
> Henning
> -----Original Message-----
> From: Stuart Brorson [mailto:sdb@xxxxxxxxxxxx]
> Sent: 23. juni 2000 21:56
> To: stds-802-3-hssg@xxxxxxxx
> Subject: RE: ONLY one ref multiplier?: PMA clock reference
> I did not intend to "beat anybody silly".  Rather, I wanted to point out
> that designing 10 Gig circuits with very low jitter is *hard*, and the
> difficulty is compounded by using lower speed reference clocks.  My friend
> from (unnamed Danish company) unwittingly proved my point by announcing that
> their 10 Gig SONET mux chip used a 155 MHz reference.  Unfortunately for
> him, that chip is known in the industry for having jitter problems.
> More importantly, my real point was that the chip vendors (and the standards
> body by extension) should not restrict the designer to using a lower speed
> (i.e. 155 MHz) clock.  IMHO, designers want to choose either 155 or 622, and
> that's the choice the 10 Gig SERDES chip designers correctly give them.
> In any event, I discovered after posting my initial message that the
> question of one vs. two clocks involved not the question of 155 vs. 622, but
> rather how to synthesize both 9.95328 GHz  and 10.3125 GHz (WAN vs. LAN)
> with only one reference clock.  Read before you post, I always say!
> Just to put my two cents into this latter discussion:  Since LAN line cards
> and WAN line cards often use different optics -- and are therefore different
> designs -- I see no reason that one needs to generate 9.95328 GHz and
> 10.3125 GHz off the same crystal.  Different boards can have different BOMs
> and call out for different oscillators.
> Stuart Brorson
> Axiowave Networks
> 100 Nickerson Road
> Marlborough, MA 01752
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