Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: ONLY one ref multiplier?: PMA clock reference


The root question is what the interface specs need to be for the XBI Tx ad Rx
data and clock signals. I'm assuming that since the data signals need to carry
10 Gbps of data that the clock signals must operate at 1/16 the data rate (i.e.
622 or 644.5 MHz).  

I assume that WHEN you say FPGA solutions you mean for the system side rather
than the Mux/Demux/CDR side of the XBI. It then seems that the possible system
side FPGA is "insulated" from the high-speed logic whose output is specified in
terms of its jitter transfer and tolerance. Since Ethernet is a point-to-point
transport, jitter specs can likely be relaxed with respect to SONET. The
magnitude of relaxation needs to be determined. Therefore, whether or not an
FPGA is used on the system side has no direct bearing on the PMA clock

Am I missing something? 

Joel Goergen wrote:
> Henning,
> My thoughts are to keep the total jitter as low as possible such that the
> available budget would allow fpga solutions to be implemented within the scope
> of the SPI4 for time to market reasons.  The fpga technology has demonstrated
> some incredible leaps over the last few years and looks really promising for
> critical time to market applications using 16x622 rates.  In such applications,
> the jitter transfer at 155Mhz may not be acceptable.  Since most transponders
> entering the market appear to support two frequencies, I would be in favor of
> defining either a min/max range, or specifically two frequencies (perfer the
> later).
> The goal, of course, is to write a standard .... but I perfer to write one that
> does not make new implementations difficult.  If, during the creation of our
> text, we can show a benifit in reduced jitter transfer, then we should define
> two clocks.  If we don't have two clocks, I am afraid we lose the engineering
> benifit of future implementations within an fpga environment.
> At this point, it would be most benificial if an fpga vendor would discuss the
> possible limitations a 155Mhz clock might have on current and future releases of
> that technology.
> Take care
> Joel Goergen
> Force10 Networks
> 1440 McCarthy blvd
> Milpitas, Ca, 95035
> Email:  joel@xxxxxxxxxxxxxxxxxxx
> Direct: (408) 571-3694
> Cell:  (612) 670-5930
> Fax:   (408) 571-3550


Best Regards,
Richard Taborek Sr.                 Phone: 408-845-6102       
Chief Technology Officer             Cell: 408-832-3957
nSerial Corporation                   Fax: 408-845-6114
2500-5 Augustine Dr.        mailto:rtaborek@xxxxxxxxxxx
Santa Clara, CA 95054