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RE: Gearbox reality check

Title: RE: Gearbox reality check


Thanks for your clarification. It made me realize I needed to provide more
clarity myself.

My budget was really for the buffering requirements in the WIS functional
block as shown in slide 3 of:

The rate adaptation between 10.000 Gb/s XGMII data rate and the ~ 9.29
Gb/s WAN PHY rate that you refer to will require buffering in either the PCS
or in the MAC layer. See slides 38, 40-41 of the presentation referenced
above. If it is in the MAC layer, it will likely be common to LAN and WAN
PHYs. Similarly, if it ends up in the PCS and vendors choose to implement
a common PCS for LAN and WAN, then it will be common to both.

For standard Ethernet maximum-length frames, the MAC/PCS rate
adaptation will require < 110 octets. (If you were to add this to the WIS
buffer, the total would be ~ 1k octets per direction).

If vendors choose to support LTL frames then, as you point out, ~ 630 octets
will be required for the MAC/PCS rate adaptation.  

Some more detail on my WIS buffer budget:

The WIS payload capacity is 9.584640 Gb/s. The 576 + 64 octet portion of
my budget absorbs the difference between that payload rate and the nominal
9.95328 Gb/s WAN PHY line rate. The 192 octets for pointer adjustments
handles any offset from nominal rates when crossing any WIS/PCS clock
boundaries. The sum, after including a few octets for jitter tolerance and a
reasonable read/write pointer separation, will come in below 1k octets per

I hope we can agree that the cost of this buffering (and the other WAN PHY
functions) is trivial and represents a very small price to pay in order for
Ethernet to gain easy access to the existing SONET/SDH-based WAN

Tim Armstrong