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    Concerning the XGMII interface, I remember at least one comment
during the plenary and I have the same reservation concerning the
extreme width and tightness of the setup and hold timing.

I would like to suggest separate clocks for each of the 8 bit lanes.
This would allow each lane to have a manageable number of tightly
coupled signals, and allow for 1 or two clocks skew between lanes.  The
Bus could easily be spread across the pins of a device enabling
distributed reference and less ground bounce. I don't see adding 3 more
pins to a 37 pin interface to be excessive.  Synchronization of the
lanes could be done using the control lines for a sync.  (i.e.. 1111
followed by 1000 on the control is start of data).

Justin Gaither                 Phone: 512-306-7292  x529
RocketChips, Inc.              Fax:   512-306-7293
500 N. Capital of TX Hwy.
Bldg 3                         email: jgaither@xxxxxxxxxxxxxxx
Austin, TX 78746               WWW: