This interface does not seem to be any harder than interfacing to DDR RAM
at the same speed. Every corner garage shop will soon be turning out
DDR RAM based motherboards soon.
Personally, I'd much rather have relatively tight timing instead of
complications in the clocking and a whole new chip to chip
protocol to spec/understand/debate/document/build.
----- Original Message -----
From: "Justin Gaither" <jgaither@xxxxxxxxxxxxxxx>
To: "802.3ae" <stds-802-3-hssg@xxxxxxxx>
Sent: Monday, July 17, 2000 3:15 PM
> Concerning the XGMII interface, I remember at least one comment
> during the plenary and I have the same reservation concerning the
> extreme width and tightness of the setup and hold timing.
> I would like to suggest separate clocks for each of the 8 bit lanes.
> This would allow each lane to have a manageable number of tightly
> coupled signals, and allow for 1 or two clocks skew between lanes. The
> Bus could easily be spread across the pins of a device enabling
> distributed reference and less ground bounce. I don't see adding 3 more
> pins to a 37 pin interface to be excessive. Synchronization of the
> lanes could be done using the control lines for a sync. (i.e.. 1111
> followed by 1000 on the control is start of data).
> Justin Gaither Phone: 512-306-7292 x529
> RocketChips, Inc. Fax: 512-306-7293
> 500 N. Capital of TX Hwy.
> Bldg 3 email: jgaither@xxxxxxxxxxxxxxx
> Austin, TX 78746 WWW: www.rocketchips.com