About two years ago I chaired FC HS-PI group which defined the 2.5
Gb/s SerDes. At the time, I was debating the parallel signaling between
HSTL and SSTL-2. SSTL-2 probably was the right technology then.
Today with current state of of CMOS technology the choice certainly would
have been HSTL (1.5 V VDDQ) with 0.75 V swing instead of SSTL-2 (2.5 V)
In most applications XGMII will be internal to the ASIC, so may be it doesn't
matter what the signaling levels are or how many clock you have. My
preference with XGMII is to have one clock on each direction.
> Date: Tue, 18 Jul 2000 13:36:54 -0700 (PDT)
> From: Howard Frazier <hfrazier@xxxxxxxxx>
> To: rronald@xxxxxxx, jgaither@xxxxxxxxxxxxxxx
> Subject: Re: XGMII
> Cc: stds-802-3-hssg@xxxxxxxx
> X-Resent-To: Multiple Recipients <stds-802-3-hssg@xxxxxxxxxxxxxxxxxx>
> X-Listname: stds-802-3-hssg
> X-Info: [Un]Subscribe requests to majordomo@xxxxxxxxxxxxxxxxxx
> X-Moderator-Address: stds-802-3-hssg-approval@xxxxxxxxxxxxxxxxxx
> As I said at the La Jolla meeting, my proposal for the XGMII timing
> is a placeholder, subject to discussion and refinement. We have
> always used the ballot and comment review process to work out a set
> of timing parameters that achieve consensus support.
> On the subject of "how many clock signals", I note that I have been
> presenting the same material since July of 1999, with one clock and
> 32 data signals in each direction. In the last year, I have heard
> lots of support for "one clock in each direction", and only three
> individual requests for "one clock for each eight bit bundle". That's
> why I keep presenting the same thing.
> My preference is for one clock in each direction, but I would be glad
> to put this up to a vote in an XGMII sub task force, if one is ever formed.
> This is a relatively straight forward decision, so I would ask
> the folks who are challenging the "one clock in each direction" position
> to put together a summary of the pros and cons, and present this at
> the September interim meeting.