I don't think the you can double your data rate today or even next year. It
is the DDR clocked interface that makes it so difficult. It cuts your time
budget in half. I am not saying it is impossible. Just that it is a very tough
interface for ASIC/FPGA and that separate clocks would make it easier to
implement. It would also make it possible to easily drive further than the
proposed 3 inches. I would not recommend it for backplane, or the like, because
of the # of pins involved but at least it is upto the designers.
Ali Ghiasi, yes if XGMII is internal to a chip then no one would use separate
clocks. But I disagree with you that XGMII will not be used externally. XGMII
is defined as and external interface, hence the electrical characteristics. If
used internally, it no longer must meet those, and a few other specifications, so
that should not be an argument. We are defining an external interface.
Steve Augusta wrote:
> As currently proposed, I don't think the XGMII forces one out of an
> FPGA or ASIC process. We have in-house designs running 64-bit
> busses with a 156 MHz ref clk. It's implemented in an FPGA.
> Granted, it's not DDR-clocked like XGMII proposes. Given the
> roadmaps that ASIC/FPGA vendors are touting, I think XGMII
> will be a challenge, but not an impossible task.
Justin Gaither Phone: 512-306-7292 x529
RocketChips, Inc. Fax: 512-306-7293
500 N. Capital of TX Hwy.
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Austin, TX 78746 WWW: www.rocketchips.com