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I understand what you are asking for, but I am against it for several reasons.

- There are several companies working this interface in both simulation and real
interface that have had great success with just the single clock.  It can be
demonstrated today by almost all the major chip suppliers.

- I really don't want to see us add the pins.  I would rather pay the skew price to
have several less clock pins (in or out).

- For longer then three inch extentions, that is what we have defined XUAI/SUPI for.
These interfaces are much better suited to longer lengths and are more robust
common-mode wise.  Eventually, the hope is that the four lane interfaces could be
brought into the MAC and XGMII won't have to be external at all.

Therefore, I would vote no for adding extra clocks to this interface.

Take care
Joel Goergen

Justin Gaither wrote:

> Steve,
>     I don't think the you can double your data rate today or even next year.  It
> is the DDR clocked interface that makes it so difficult.  It cuts your time
> budget in half.  I am not saying it is impossible.  Just that it is a very tough
> interface for ASIC/FPGA and that separate clocks would make it easier to
> implement.   It would also make it possible to easily drive further than the
> proposed 3 inches.  I would not recommend it for backplane, or the like, because
> of the # of pins involved but at least it is upto the designers.
> Ali Ghiasi, yes if  XGMII is internal to a chip then no one would use separate
> clocks.  But I disagree with you that XGMII will not be used externally.  XGMII
> is defined as and external interface, hence the electrical characteristics.  If
> used internally, it no longer must meet those, and a few other specifications, so
> that should not be an argument.  We are defining an external interface.
> Justin
> Steve Augusta wrote:
> > Justin,
> >
> > As currently proposed, I don't think the XGMII forces one out of an
> > FPGA or ASIC process.  We have in-house designs running 64-bit
> > busses with a 156 MHz ref clk.  It's implemented in an FPGA.
> > Granted, it's not DDR-clocked like XGMII proposes.  Given the
> > roadmaps that ASIC/FPGA vendors are touting, I think XGMII
> > will be a challenge, but not an impossible task.
> >
> > Steve
> >