Question about Open-loop control in XGMII Mac....
I have a question about the open-loop control presentation
In this figure I assume the tx_clk is byte clock and if so then
it must be running at 8*156.25 Mhz. Is the intention to run the MAC
at this speed? I thought specifying the XGMII 156 DDR is just not
for reducing the interconnect speed but also the MAC can be run at
lower speed. If the MAC is assuming lower speeds (156/312 Mhz)
Then how would one count 'd13 bytes with these clocks?
Also, if you need to count only 'd13 why do you need 5-bit counter?
If these are already discussed and resolved could you please point me
to the material or is there something I am missing here.