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(Another) Question Regarding Open-Loop Control Mechanism

When the MAC device and the PHY device are driven by a different clock
source, How does  Clock Tolerance Compensation between the two done? 
(That is, since the max difference between the two is 200ppm, then the MAC
may always adjust the rate to the nominal rate - 200ppm? And if so: Is it
acceptable ?)

Sorry if this was asked before.