In a previous email thread, we debated the merits of using
a single clock in each direction on the XGMII, versus using
4 (frequency locked, but phase independent) clocks in each direction,
with a clock dedicated to each of the four "lanes".
Without repeating the discussion, it is safe to summarize that
the majority opinion (from among those who expressed an opinion)
was to stay with one clock in each direction.
So, I would like to toss out another question for your consideration.
Should we use a two phase clock? Clock and ClockBar?
Some designers have suggested that this will make the ASIC and
system timing more managable, because it is difficult to get
symetric drive strengths from the clock output buffers, and
the asymetry degrades the timing. With a two phase clock, you
would still have asymetry on the data signals, but at least
you won't have to account for the asymetry on the clock.
At first blush, this seems like a modest addition. One more pin
in each direction.
Any opinions out there?
Cisco Systems, Inc.