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Re: XGMII Clocks

Hi Howard,

At these speeds I think it should be almost mandatory to use a 
differential clock  (a differntial clock is slightly different
than a 2-phase clock).  The differential input will allow
at least the reference input to be immune from power supply 
induced threshold variation.  Because the parallel outputs are
all single-ended, when they switch (with different data patterns)
there will be differing amounts of internal power and ground 
shifting that occur.  

Without a differential clock, your setup/hold window changes 
not only with respect to power supply noise and board-level 
crosstalk, but also with respect to the phase of the recovered 
data relative to the transition of the clock input.  As an example,
if the recoverd-data parallel-outputs change at the same time that
the clock input changes, there will be more timing variability
than when the recoverd-data parallel-outputs change when the
clock is stable.

Differntial clocks have been used for many years in precision clock
and high-speed signaling.  I strongly support your suggestion, but 
with the provision that this be a differential clock input rather 
than just a two-phase input.


Ed Grivna
Cypress Semiconductor

> In a previous email thread, we debated the merits of using
> a single clock in each direction on the XGMII, versus using
> 4 (frequency locked, but phase independent) clocks in each direction, 
> with a clock dedicated to each of the four "lanes".
> Without repeating the discussion, it is safe to summarize that
> the majority opinion (from among those who expressed an opinion)
> was to stay with one clock in each direction.
> So, I would like to toss out another question for your consideration.
> Should we use a two phase clock? Clock and ClockBar?
> Some designers have suggested that this will make the ASIC and
> system timing more managable, because it is difficult to get
> symetric drive strengths from the clock output buffers, and
> the asymetry degrades the timing.  With a two phase clock, you
> would still have asymetry on the data signals, but at least
> you won't have to account for the asymetry on the clock.
> At first blush, this seems like a modest addition. One more pin
> in each direction.
> Any opinions out there?
> Howard Frazier
> Cisco Systems, Inc.