Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

XGMII clocks and timing...


I agree that this would help relieve the clock asymmetry.
But there is another dimension of this problem the 
source synchronous vs source centered. 

If not impossible, it is really very tough to get 
source centered clocks out of an CMOS ASIC

May be wild idea but if source centered is preferred
then I would suggest that it should be done by single
device (either XGXS layer or MAC in ASIC). Which means
on receive source centered and on transmit source sync, 
if XGXS layer does it or vice-versa.

Why? Because the XGXS (or lower layer) does 
source centered clocking in receive so it has the 
circuitry and it can use same circuit in transmit 
and get source sync and internally does 
source centered clocking.


At 09:30 AM 09/06/2000 -0700, you wrote:
>In a previous email thread, we debated the merits of using
>a single clock in each direction on the XGMII, versus using
>4 (frequency locked, but phase independent) clocks in each direction, 
>with a clock dedicated to each of the four "lanes".
>Without repeating the discussion, it is safe to summarize that
>the majority opinion (from among those who expressed an opinion)
>was to stay with one clock in each direction.
>So, I would like to toss out another question for your consideration.
>Should we use a two phase clock? Clock and ClockBar?
>Some designers have suggested that this will make the ASIC and
>system timing more managable, because it is difficult to get
>symetric drive strengths from the clock output buffers, and
>the asymetry degrades the timing.  With a two phase clock, you
>would still have asymetry on the data signals, but at least
>you won't have to account for the asymetry on the clock.
>At first blush, this seems like a modest addition. One more pin
>in each direction.
>Any opinions out there?
>Howard Frazier
>Cisco Systems, Inc.