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Re: FW: XGMII Clocks


I agree with you that the "best bang for the buck" insofar as XGMII
interface operations goes may be to lower voltage swings and better
match impedance.

The alternative, but perhaps more complex approach, would be to retain
the current source centered clocking and have the XGMII receiver adjust
perform precise phase positioning in an implementation. This alternative
is implementation dependent regardless of the clock I/O signal

In any case, two-phase or differential clocks DDR clocking schemes do
not seem to help. In addition, they both cost pins.

Best Regards,

Curt Berg wrote:
> Hi,
> With two phase clocks you trade duty cycle problem against
> managing two clocks and two paths. You still need to accurately
> put the second clocks posedge in the middle, and you have the same
> "duty cycle" distrotion on data. Not easy to put the 2nd pos edge
> in the middle if you don't start with a 2x clock. Well if you have
> a 2x clock then it is easy to generate a symmetric clock !
> The max gitter between clock and data is what kills you.
> It is not enought to run best case and worst case sims, instead
> weak p strong n, and strong p weak n, will make your make your
> live difficult. Basically standard ASIC STA is not useful to analys
> this problem ! Most bang for the buck is a lower voltage swing,
> and more matched impedance. All high speed SRAMs, with DDR (that I know
> of) have gone to HSTL, with impedance controlled drivers for very good
> reasons !!
> -Curt Berg-
> Extreme Networks
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