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Regarding the choice of IO standard for XGMII, I'd like to offer the
following perspective from an FPGA vendor.

Currently, Xilinx supports HSTL Class 1, 3 and 4 but Altera only supports
HSTL Class 1.  Actel does not support HSTL at the moment but, if at all
possible, would like to ensure that products in the pipeline can support

If interoperability is a goal, out  of the shoot, I'd say you're stuck with
HSTL Class 1 if you want to make the switch to HSTL from SSTL.  

If that's not enough, here's more:

CSIX ( a backplane standards org ) has selected HSTL
Class 1.  Might be relevant to the line card board designer ... minimizing
the IO standards he has to deal with. 

The difference among classes is primarily drive strengths which are spec'ed
to support different termination schemes:

HSTL Class 1: IOH -8,   IOL 8
HSTL Class 2: IOH -16, IOL 16
HSTL Class 3: IOH -8,   IOL 24
HSTL Class 4: IOH -8,   IOL 48

HSTL Class 2 is onerous to support for an FPGA vendor because of the
required size of the pull-up.  Similarly, Class 3 and Class 4 require large
pull-downs that are expensive to support in a general purpose FPGA.

VCCO for all HSTL classes is 1.5 V +/- 0.1 V.  There is no 1.8 volt HSTL
standard that I am aware of (BTW, I'm not an IO guy so I could be lying
about all of this stuff).

I also understand that there are other tricky (but not unsolvable) things
involved with design of the diff amp based around the requirement for a Vref
(min) of 0.68V.  That doesn't give much headroom in 1.5 volt and lower

So, if I was old enough to vote, I would vote for HSTL Class 1 over other
HSTL standards.  


Ted Speers
Sr. Manager, Strategic Marketing