RE: XGMII: HSTL Classes
A. I support HSTL Class 1. Reasons as follows:
1. It is the only HSTL class that is supported by more than one FPGA
vendor. I suspect the reason for this has to do with the economics of
making FPGAs and the the large driver sizes needed for HSTL Class 3 and 4
(VOL = 24 and 48 mA respectively). FPGA vendors try to make "one size fits
all" devices. At some point, the cost of achieving this goal becomes too
burdensome and a particular IO standard or a feature is dropped, never to
return due to the investment in a whole family of FPGAs. HSTL Class 2 is
not supported by any FPGA vendor, possibly due to the large Pull-up required
(VOH = - 16 mA).
2. CSIX, a backplane switching standard, uses HSTL Class 1.
B. "Shoot" should be "chute."
> -----Original Message-----
> From: Geoff Thompson [SMTP:gthompso@xxxxxxxxxxxxxxxxxx]
> Sent: Monday, September 18, 2000 12:14 PM
> To: Speers, Ted
> Cc: 'stds-802-3-hssg@xxxxxxxx'
> Subject: Re: XGMII: HSTL Classes
> Whether your company or some other vendor happens to support a particular
> interface specification is just a little too close to a conversation that
> could be construed as one that was related "as to how to carve up a
> i.e. not appropriate for the standards reflector.
> Please rephrase.
> At 04:23 PM 9/15/00 -0700, Speers, Ted wrote:
> >Regarding the choice of IO standard for XGMII, I'd like to offer the
> >following perspective from an FPGA vendor.
> >Currently, Xilinx supports HSTL Class 1, 3 and 4 but Altera only supports
> >HSTL Class 1. Actel does not support HSTL at the moment but, if at all
> >possible, would like to ensure that products in the pipeline can support
> >If interoperability is a goal, out of the shoot, I'd say you're stuck
> >HSTL Class 1 if you want to make the switch to HSTL from SSTL.
> >If that's not enough, here's more:
> >CSIX ( a backplane standards org http://www.csix.org ) has selected HSTL
> >Class 1. Might be relevant to the line card board designer ...
> >the IO standards he has to deal with.
> >The difference among classes is primarily drive strengths which are
> >to support different termination schemes:
> >HSTL Class 1: IOH -8, IOL 8
> >HSTL Class 2: IOH -16, IOL 16
> >HSTL Class 3: IOH -8, IOL 24
> >HSTL Class 4: IOH -8, IOL 48
> >HSTL Class 2 is onerous to support for an FPGA vendor because of the
> >required size of the pull-up. Similarly, Class 3 and Class 4 require
> >pull-downs that are expensive to support in a general purpose FPGA.
> >VCCO for all HSTL classes is 1.5 V +/- 0.1 V. There is no 1.8 volt HSTL
> >standard that I am aware of (BTW, I'm not an IO guy so I could be lying
> >about all of this stuff).
> >I also understand that there are other tricky (but not unsolvable) things
> >involved with design of the diff amp based around the requirement for a
> >(min) of 0.68V. That doesn't give much headroom in 1.5 volt and lower
> >So, if I was old enough to vote, I would vote for HSTL Class 1 over other
> >HSTL standards.
> >Ted Speers
> >Sr. Manager, Strategic Marketing