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Clause 33 comments


Just a few comments from reading clause 33: - page 69, line 48
  While the reset process is not yet complete, the PMA/PMD is
  not required to accept a write transaction to the control
  register. Why is this limited to the control register? Why
  aren't all the registers included? - pages 80&81
  Should we add a de-skew/lane alignment bit to this

33.3.5 - page 84
  When the address is 65535 and the access is a
  post_xxx_increment, is the next address 0? - page 85
  Does this protocol support preamble suppression?


Benjamin Brown
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