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Source centered vs source sync


One problem I found in implementing source synchronous design is that we need
to adjust timing by inserting buffers. When worst case to best case ratio 
of delays
are high, this becomes a tough problem to solve (especially when available 
time is
a few ns). In centered clock case, this does not become a problem. There may be
still buffers in clock/data paths but they track each other under various 
To take example of FC vs. GMII timings, I have found GMII timings (which are
source sync.) much difficult to implement compared to FC (which is source 


At 01:25 AM 9/26/00 -0700, you wrote:

Best Regards,

Devendra Tripathi
Vitesse Semoconductor Corporation
3100 De La Cruz Boulevard
Santa Clara, CA  95054
Phone: (408) 986-4380 Ext 103
Fax:	(408) 986-6050