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Clause 49 comments

1. Figure 49-4--" PCS Receive Bit Ordering".
     I think the direction arrows should be :
             from Serial transmission order --> rx_data_unit<15>,
             from rx_data_unit<0> ----> the left side of "Gearbox",
             from the right side of "Gearbox" ----> RxB<65> (the right
side of "Receive block"),
             from bit0 of S0  ----> Descrambler ----> bit7 of D7(the
right side of Ouput of descramblerfunction).

2. Figure 49-8--"Lock state machine" .
    a. I think come out of the state "SLIP", you should reset the
64frames_timer and 125us_timer.  Because in the
        "SLIP" state and the states before "SLIP", mt_inalid_cnt and
hi_ber_cnt should not be carried over.
    b. The condition for the "NO_FRAME_LOCK" --> "SLIP", I think it's
better to use !mt_valid, rather than
        "bad_mt_gt_32=true",  we can acquire Frame_Lock much faster.

3. Figure 49-9--"BER Monitor State Machine"
    a. This diagram is not clear.
        I think "M1" should not be an independent state. Assume using
frame clock toimplement, that means every
        clock you need to see if "mt_valid" is true or false,  then M1
and M2, or M1 and M3 must happend in a
        single clock. Further,  mt_valid = true or false,
64frames_time_done and 125us_timer_done, these 3 events
        could happend at the  same clock, that means M2, M3, M4 and M5
can not be independent state.
    b. I think there is no need for mt_valid_cnt. Because you already
have mt_invalid_cnt and 64frames_timer,
         when 64frames_timer_done, mt_invalid_cnt==0 means good_mt_eq_64
= true.
    c. My suggestion:
         if ((mt_invalid_cnt == 32) && (!mt_valid)), then set
bad_mt_gt_32 = true, reset 64frames_timer, reset
         if ((hi_ber== 15) &&(!mt_valid)), then set hi_ber=true, reset
125us_timer, reset hi_ber_cnt.