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Clause 51 (XSBI) questions

Justin, et al

I have some comments and questions regarding clause
51, the XSBI interface.

1. Table 5-6 of the draft 1.0 specifies a maximum delay
variation of 30 ns p-p.  Does the condition (frequency <
1kHz) refer to the frequency of the delay variation
changing? or is there some other meaning.

2. In section 51.3.1 it says: "The falling edge of
PMA_TXCLK_SRC<0,1> is used by the PCS to derive
PMA_TX_CLK<0,1>.  Does this mean we are meant to invert
PMA_TXCLK_SRC to create PMA_TX_CLK?  or is it meant to be
a requirement that if a PLL is used, the PLL uses the
negative TXCLK_SRC edge for phase alignment?

3. The draft spec specifies the transmit direction timing
at the PMA inputs.  There are no numbers for the PCS outputs.
Furthermore, the values given for setup and hold are 50 ps
smaller than OIF SFI-4 specifies at the SERDES input.  Will
802.3 ever specify timing constraints at the PCS output for
the transmit direction and PMA input for the receive direction?

4. Is there a reason the edges are reversed between OIF SFI-4
and the draft 1.0?  Specifically, SFI-4 specifies the Rx data
valid around the RX_CLK positive edge while the draft
specifies Rx data valid around the RX_CLK falling edge.  I
realize you can simply switch your differential inputs to
achieve the switch.

Erik Trounce